Using fully-accelerated hardware-based video decoding and encoding with FFMPEG on Jetson Nano

Autonomous Machines Jetson & Embedded Systems Jetson Nano
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1

Hello,

What is generation of nano (945-13450-0000-100) ?
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I am trying to use FFmpeg GPU HW-Acceleration. Where in the table below?

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The video encoding / decoding result shown in the Technical Specifications below is based on using ISP (Image signal processing). Is it correct to use NVDEC and NVENC shown in the figure below?

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I know that I can use fully-accelerated hardware-based video decoding and encoding separate from the Cuda core. Is it correct?

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Thank you.

3

Hi,
We don’t support ffmpeg with hardware acceleration on Jetson platforms. There is a community contribution. Please check FAQ
Q: Is hardware acceleration enabled in ffmpeg?

You may consider to use tegra_multimedia_api or gstreamer.

NVENC and NVDEC are independent hardware engines for video encoding/decoding. Please check Tegra X1 SoC Technical Reference Manual in
https://developer.nvidia.com/embedded/downloads#?search=trm