Using PCIe Bridge with SATA Controller

sumin.lee · March 21, 2022, 11:05pm

Hello,

We are using PCIe bridge with SATA Multi controller on Custrom Board for Jetson Nano .
It looks PCI Interface is recognized.
dmesg.txt (57.9 KB)

[    0.490259] iommu: Adding device 1003000.pcie to group 24
[    0.490312] platform 1003000.pcie: domain=ffffffc0f95209d8 allocates as[0]=ffffffc0f94244b8
[    1.019045] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.3, lane = pcie-0, function = pcie-x1
[    1.019133] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.4, lane = pcie-1, function = pcie-x4
[    1.019224] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.5, lane = pcie-2, function = pcie-x4
[    1.019312] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.6, lane = pcie-3, function = pcie-x4
[    1.019406] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.7, lane = pcie-4, function = pcie-x4
[    1.019494] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.8, lane = pcie-5, function = xusb
[    1.019583] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.9, lane = pcie-6, function = xusb
[    1.029284] tegra-pcie 1003000.pcie: 4x1, 1x1 configuration
[    1.030557] tegra-pcie 1003000.pcie: PCIE: Enable power rails
[    1.030913] tegra-pcie 1003000.pcie: probing port 0, using 4 lanes
[    1.034680] tegra-pcie 1003000.pcie: probing port 1, using 1 lanes
[    1.568043] tegra-pcie 1003000.pcie: PCI host bridge to bus 0000:00
[    1.568051] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.568058] pci_bus 0000:00: root bus resource [mem 0x13000000-0x1fffffff]
[    1.568063] pci_bus 0000:00: root bus resource [mem 0x20000000-0x3fffffff pref]
[    1.568069] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.568098] pci 0000:00:01.0: [10de:0fae] type 01 class 0x060400
[    1.568169] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    1.568442] pci 0000:00:02.0: [10de:0faf] type 01 class 0x060400
[    1.568522] pci 0000:00:02.0: PME# supported from D0 D1 D2 D3hot D3cold
[    1.568751] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    1.568760] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    1.568891] pci 0000:01:00.0: [12d8:2308] type 01 class 0x060400
[    1.569095] pci 0000:01:00.0: supports D1 D2
[    1.569100] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    1.581896] pci 0000:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    1.582066] pci 0000:02:01.0: [12d8:2308] type 01 class 0x060400
[    1.582212] pci 0000:02:01.0: supports D1 D2
[    1.582216] pci 0000:02:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    1.582485] pci 0000:02:02.0: [12d8:2308] type 01 class 0x060400
[    1.582619] pci 0000:02:02.0: supports D1 D2
[    1.582623] pci 0000:02:02.0: PME# supported from D0 D1 D2 D3hot D3cold
[    1.582954] pci 0000:02:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    1.582965] pci 0000:02:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    1.583082] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
[    1.583219] pci 0000:04:00.0: [8086:157c] type 00 class 0x020000
[    1.583248] pci 0000:04:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[    1.583274] pci 0000:04:00.0: reg 0x18: [io  0x0000-0x001f]
[    1.583289] pci 0000:04:00.0: reg 0x1c: [mem 0x00000000-0x00003fff]
[    1.583453] pci 0000:04:00.0: PME# supported from D0 D3hot D3cold
[    1.593909] pci_bus 0000:04: busn_res: [bus 04-ff] end is updated to 04
[    1.593918] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 04
[    1.593928] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 04
[    1.594062] pci 0000:05:00.0: [10ec:8168] type 00 class 0x020000
[    1.594085] pci 0000:05:00.0: reg 0x10: [io  0x0000-0x00ff]
[    1.594112] pci 0000:05:00.0: reg 0x18: [mem 0x00000000-0x00000fff 64bit pref]
[    1.594130] pci 0000:05:00.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
[    1.594255] pci 0000:05:00.0: supports D1 D2
[    1.594260] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    1.605887] pci_bus 0000:05: busn_res: [bus 05-ff] end is updated to 05
[    1.605976] pci 0000:00:01.0: BAR 14: assigned [mem 0x13000000-0x133fffff]
[    1.605985] pci 0000:00:01.0: BAR 15: assigned [mem 0x20000000-0x203fffff 64bit pref]
[    1.605994] pci 0000:00:02.0: BAR 15: assigned [mem 0x20400000-0x204fffff 64bit pref]
[    1.606000] pci 0000:00:01.0: BAR 13: assigned [io  0x1000-0x2fff]
[    1.606005] pci 0000:00:02.0: BAR 13: assigned [io  0x3000-0x3fff]
[    1.606014] pci 0000:01:00.0: BAR 14: assigned [mem 0x13000000-0x133fffff]
[    1.606021] pci 0000:01:00.0: BAR 15: assigned [mem 0x20000000-0x203fffff 64bit pref]
[    1.606026] pci 0000:01:00.0: BAR 13: assigned [io  0x1000-0x2fff]
[    1.606035] pci 0000:02:01.0: BAR 14: assigned [mem 0x13000000-0x131fffff]
[    1.606042] pci 0000:02:01.0: BAR 15: assigned [mem 0x20000000-0x201fffff 64bit pref]
[    1.606049] pci 0000:02:02.0: BAR 14: assigned [mem 0x13200000-0x133fffff]
[    1.606055] pci 0000:02:02.0: BAR 15: assigned [mem 0x20200000-0x203fffff 64bit pref]
[    1.606061] pci 0000:02:01.0: BAR 13: assigned [io  0x1000-0x1fff]
[    1.606066] pci 0000:02:02.0: BAR 13: assigned [io  0x2000-0x2fff]
[    1.606072] pci 0000:02:01.0: PCI bridge to [bus 03]
[    1.606079] pci 0000:02:01.0:   bridge window [io  0x1000-0x1fff]
[    1.606087] pci 0000:02:01.0:   bridge window [mem 0x13000000-0x131fffff]
[    1.606095] pci 0000:02:01.0:   bridge window [mem 0x20000000-0x201fffff 64bit pref]
[    1.606107] pci 0000:04:00.0: BAR 0: assigned [mem 0x13200000-0x1321ffff]
[    1.606118] pci 0000:04:00.0: BAR 3: assigned [mem 0x13220000-0x13223fff]
[    1.606127] pci 0000:04:00.0: BAR 2: assigned [io  0x2000-0x201f]
[    1.606137] pci 0000:02:02.0: PCI bridge to [bus 04]
[    1.606143] pci 0000:02:02.0:   bridge window [io  0x2000-0x2fff]
[    1.606151] pci 0000:02:02.0:   bridge window [mem 0x13200000-0x133fffff]
[    1.606158] pci 0000:02:02.0:   bridge window [mem 0x20200000-0x203fffff 64bit pref]
[    1.606167] pci 0000:01:00.0: PCI bridge to [bus 02-04]
[    1.606172] pci 0000:01:00.0:   bridge window [io  0x1000-0x2fff]
[    1.606180] pci 0000:01:00.0:   bridge window [mem 0x13000000-0x133fffff]
[    1.606188] pci 0000:01:00.0:   bridge window [mem 0x20000000-0x203fffff 64bit pref]
[    1.606197] pci 0000:00:01.0: PCI bridge to [bus 01-04]
[    1.606202] pci 0000:00:01.0:   bridge window [io  0x1000-0x2fff]
[    1.606208] pci 0000:00:01.0:   bridge window [mem 0x13000000-0x133fffff]
[    1.606214] pci 0000:00:01.0:   bridge window [mem 0x20000000-0x203fffff 64bit pref]
[    1.606224] pci 0000:05:00.0: BAR 4: assigned [mem 0x20400000-0x20403fff 64bit pref]
[    1.606241] pci 0000:05:00.0: BAR 2: assigned [mem 0x20404000-0x20404fff 64bit pref]
[    1.606257] pci 0000:05:00.0: BAR 0: assigned [io  0x3000-0x30ff]
[    1.606265] pci 0000:00:02.0: PCI bridge to [bus 05]
[    1.606270] pci 0000:00:02.0:   bridge window [io  0x3000-0x3fff]
[    1.606278] pci 0000:00:02.0:   bridge window [mem 0x20400000-0x204fffff 64bit pref]
[    1.606608] pcieport 0000:00:01.0: Signaling PME through PCIe PME interrupt
[    1.606613] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[    1.606617] pci 0000:02:01.0: Signaling PME through PCIe PME interrupt
[    1.606621] pci 0000:02:02.0: Signaling PME through PCIe PME interrupt
[    1.606625] pci 0000:04:00.0: Signaling PME through PCIe PME interrupt
[    1.606631] pcie_pme 0000:00:01.0:pcie001: service driver pcie_pme loaded
[    1.606759] aer 0000:00:01.0:pcie002: service driver aer loaded
[    1.606967] pcieport 0000:00:02.0: Signaling PME through PCIe PME interrupt
[    1.606972] pci 0000:05:00.0: Signaling PME through PCIe PME interrupt
[    1.606979] pcie_pme 0000:00:02.0:pcie001: service driver pcie_pme loaded
[    1.607092] aer 0000:00:02.0:pcie002: service driver aer loaded
[    1.667158] ehci-pci: EHCI PCI platform driver
[    1.667207] ohci-pci: OHCI PCI platform driver

But We can’t access any sata storage.

There is other information.
lspci -vv.txt (31.4 KB)
fdisk -l.txt (6.3 KB)
Hardware.html (28.5 KB)

I wonder I have to do something for device tree or kernel module.

Manikanta · March 24, 2022, 5:51pm

Hi,

I don’t see sata device in lspci output. Share you hardware topology details and match it with “lspci -tv”. Then let me know where(BDF) it supposed to be enumerated.

Thanks,
Manikanta

sumin.lee · March 31, 2022, 10:45pm

Hello,

We have to use 2 port of PCI on Nano Module.
So, we are using external PCIe bridge.

Manikanta · April 1, 2022, 3:33am

Hi,

lspci output doesn’t link it is from Nano, it will have only one PCIe domain, but I see 3 here.
It doesn’t match with your previous logs.

Thanks,
Manikanta

Manikanta · April 1, 2022, 3:37am

Hi,

In the previous lspci -vvv logs, I see that switch downstream port of SATA mulit has DLavtice-. Which mean mean link between switch DP and SATA didn’t establish. This is out of Tegra scope, please debug from switch/SATA side.

Thanks,
Manikanta

sumin.lee · April 1, 2022, 3:43am

Thanks, I would check it.

system · April 27, 2022, 3:52am

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.