Hello JerryChang,
For this dtsi file,the clk_out_3 clock rate will is MUST 24.0MHz, is rigth?
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_3>;
clock-names = "clk_out_3";
clock-frequency = <24000000>;
mclk = "clk_out_3";
hello sensor_test,
please check my comment #20, had you tried to configure the clock-frequency by your own already?
thanks
Hello JerryChang,
1.I only at dtsi file configure clock-frequency,please see as below:
Is it right?
host1x {
i2c@546c0000 {
imx219_a@10 {
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
/* mclk-index indicates the index of the */
/* mclk-name with in the clock-names array */
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_3>;
clock-names = "clk_out_3";
clock-frequency = <24000000>;
...
mode0 { //
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_a";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
2.If have some other way to configure the clock-frequency,please tell me.
hello sensor_test,
again,
please check my comment #20,
thanks
Hello JerryChang,
Please see my TX1 ALL clk info.
root@tegra-ubuntu:~# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate req_rate accuracy phase
----------------------------------------------------------------------------------------------------------------------
dfllCPU_out 1 1 1224000000 1224000000 0 0
*[ default_freq 0]
cclk_g 1 1 1224000000 0 0 0
*[ default_freq 0]
vimclk_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s4_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s3_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s2_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s1_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
i2s0_sync 0 0 1411200 1411200 0 0
*[ default_freq 0]
dmic3_sync_clk_mux 0 0 1411200 0 0 0
*[ default_freq 0]
dmic3_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dmic2_sync_clk_mux 0 0 1411200 0 0 0
*[ default_freq 0]
dmic2_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
dmic1_sync_clk_mux 0 0 1411200 0 0 0
*[ default_freq 0]
dmic1_sync_clk 0 0 1411200 0 0 0
*[ default_freq 0]
spdif_in_sync 0 0 24576000 24576000 0 0
*[ default_freq 0]
spdif_mux 0 0 24576000 0 0 0
*[ default_freq 0]
spdif 0 0 24576000 0 0 0
*[ default_freq 0]
spdif_doubler 0 0 49152000 0 0 0
*[ default_freq 0]
spdif_div 0 0 49152000 0 0 0
*[ default_freq 0]
spdif_2x 0 0 49152000 0 0 0
*[ default_freq 0]
audio4_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio4 0 0 24576000 0 0 0
*[ default_freq 0]
audio3_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio3 0 0 24576000 0 0 0
*[ default_freq 0]
audio2_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio2 0 0 24576000 0 0 0
*[ default_freq 0]
audio1_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio1 0 0 24576000 0 0 0
*[ default_freq 0]
audio0_mux 0 0 24576000 0 0 0
*[ default_freq 0]
audio0 0 0 24576000 0 0 0
*[ default_freq 0]
pd2vi 0 0 0 0 0 0
*[ default_freq 0]
sor1_brick 0 0 0 0 0 0
*[ default_freq 0]
clk_32k 1 1 32768 32768 0 0
*[ default_freq 0]
blink_override 0 0 32768 32768 0 0
*[ default_freq 0]
blink 0 0 32768 32768 0 0
*[ default_freq 0]
rtc 1 1 32768 32768 0 0
*[ default_freq 0]
osc 4 4 38400000 38400000 0 0
*[ default_freq 0]
usb2_hsic_trk 0 0 9600000 9600000 0 0
*[ default_freq 0]
hsic_trk 0 0 9600000 0 0 0
*[ default_freq 0]
usb2_trk 0 0 9600000 0 0 0
*[ default_freq 0]
xusb_gate 1 1 38400000 38400000 0 0
*[ default_freq 0]
pll_mb 0 0 1331200000 1600000000 0 0
*[ default_freq 0]
pll_mb_ud 0 0 1331200000 1331200000 0 0
*[ default_freq 0]
pll_m 1 1 1065600000 800000000 0 0
*[ default_freq 0]
pll_m_ud 1 1 1065600000 1065600000 0 0
*[ default_freq 0]
emc 3 3 1065600000 800000000 0 0
*[ default_freq 0]
emc_master 1 1 1065600000 1056000000 0 0
*[ default_freq 0]
bwmgr.emc 1 1 1065600000 1056000000 0 0
*[ default_freq 0]
pcie.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
ape.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
vic.shared_emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
vic.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
vib.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
via.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
tsecb.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
nvdec.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
nvjpg.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
gr3d.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
sdmmc3.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
disp2.la.emc 0 0 1065600000 0 0 0
*[ default_freq 0]
disp1.la.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
xusb.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
ispb.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
ispa.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
battery.emc 0 0 1600000000 1600000000 0 0
*[ default_freq 0]
edp.emc 0 0 1600000000 1600000000 0 0
*[ default_freq 0]
override.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
floor.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
cap.throttle.emc 0 0 1600000000 1600000000 0 0
*[ default_freq 0]
cap.emc 0 0 1600000000 1600000000 0 0
*[ default_freq 0]
iso.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
camera.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
sdmmc4.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
tsec.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
mon.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
usb3.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
usb2.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
usb1.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
usbd.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
disp2.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
disp1.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
cpu.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
avp.emc 0 0 1065600000 800000000 0 0
*[ default_freq 0]
mc 4 4 266400000 200000000 0 0
*[ default_freq 0]
mc_cdpa 1 1 266400000 200000000 0 0
*[ default_freq 0]
mc_ccpa 1 1 266400000 200000000 0 0
*[ default_freq 0]
mc_cbpa 1 1 266400000 200000000 0 0
*[ default_freq 0]
mc_capa 1 1 266400000 200000000 0 0
*[ default_freq 0]
pll_ref 5 5 38400000 38400000 0 0
*[ default_freq 0]
pll_x 0 0 691200000 691200000 0 0
*[ default_freq 0]
pll_x_out0 0 0 345600000 345600000 0 0
*[ default_freq 0]
pll_a1 0 0 307200000 307200000 0 0
*[ default_freq 0]
aclk 0 0 307200000 19200000 0 0
*[ default_freq 0]
adsp 0 0 307200000 0 0 0
*[ default_freq 0]
adsp_neon 0 0 307200000 0 0 0
*[ default_freq 0]
abus 0 0 307200000 307200000 0 0
*[ default_freq 0]
override.abus 0 0 307200000 307200000 0 0
*[ default_freq 0]
cap.vcore.abus 0 0 844800000 4294967295 0 0
*[ default_freq 0]
adsp.cpu.abus 0 0 307200000 307200000 0 0
*[ default_freq 0]
pll_a 2 2 338687500 338688000 0 0
*[ default_freq 0]
pll_a_out0_div 1 1 45158334 61440000 0 0
*[ default_freq 0]
pll_a_out0 2 2 45158334 45158400 0 0
*[ default_freq 0]
d_audio 0 0 45158334 45158400 0 0
*[ default_freq 0]
d_audio_slcg_ovr 0 0 45158334 19200000 0 0
*[ default_freq 0]
i2s4 0 0 6021112 1536000 0 0
*[ default_freq 0]
i2s3 0 0 6021112 1536000 0 0
*[ default_freq 0]
i2s2 0 0 6021112 1536000 0 0
*[ default_freq 0]
i2s1 0 0 6021112 1536000 0 0
*[ default_freq 0]
i2s0 0 0 1411198 1411200 0 0
*[ default_freq 0]
extern1 3 3 11289584 11289600 0 0
*[ default_freq 0]
clk_out_1_mux 2 2 11289584 19200000 0 0
*[ default_freq 0]
clk_out_1 1 1 11289584 19200000 0 0
*[ default_freq 0]
dmic1 0 0 11289584 3072000 0 0
*[ default_freq 0]
dmic2 0 0 11289584 3072000 0 0
*[ default_freq 0]
dmic3 0 0 11289584 3072000 0 0
*[ default_freq 0]
pll_a_out_adsp 0 0 338687500 0 0 0
*[ default_freq 0]
pll_a_out0_out_adsp 0 0 338687500 0 0 0
*[ default_freq 0]
pllg_ref 0 0 38400000 38400000 0 0
*[ default_freq 0]
gpcclk 0 0 76800000 76800000 0 0
*[ default_freq 0]
gbus 0 0 76800000 76800000 0 0
*[ default_freq 0]
floor.profile_gbus 0 0 76800000 0 0 0
*[ default_freq 0]
floor.gbus 0 0 76800000 0 0 0
*[ default_freq 0]
override.gbus 0 0 76800000 0 0 0
*[ default_freq 0]
cap.profile_gbus 0 0 1300000000 1300000000 0 0
*[ default_freq 0]
cap.throttle_gbus 0 0 1300000000 1300000000 0 0
*[ default_freq 0]
cap.vgpu.gbus 0 0 1300000000 1300000000 0 0
*[ default_freq 0]
edp.gbus 0 0 998400000 998400000 0 0
*[ default_freq 0]
cap.gbus 0 0 1300000000 1300000000 0 0
*[ default_freq 0]
gm20b.gbus 0 0 76800000 76800000 0 0
*[ default_freq 0]
gpu 0 0 38400000 38400000 0 0
*[ default_freq 0]
pll_p 18 22 408000000 408000000 0 0
*[ default_freq 0]
pwm 1 1 48000000 48000000 0 0
*[ default_freq 0]
vii2c 0 1 81600000 83200000 0 0
*[ default_freq 0]
cilab 0 0 102000000 102000000 0 0
*[ default_freq 0]
cilcd 0 0 102000000 102000000 0 0
*[ default_freq 0]
cile 0 0 102000000 102000000 0 0
*[ default_freq 0]
extern3 0 0 12000000 24000000 0 0
*[ default_freq 0]
clk_out_3_mux 0 0 12000000 19200000 0 0
*[ default_freq 0]
clk_out_3 0 0 12000000 12000000 0 0
*[ default_freq 0]
clk72mhz 0 0 68000000 68000000 0 0
*[ default_freq 0]
sdmmc2 0 0 204000000 204000000 0 0
*[ default_freq 0]
i2c6 0 1 81600000 83200000 0 0
*[ default_freq 0]
i2c4 0 1 20400000 20800000 0 0
*[ default_freq 0]
ape 1 1 25500000 25500000 0 0
*[ default_freq 0]
ape_master 0 0 25500000 9600000 0 0
*[ default_freq 0]
override.ape 0 0 25500000 9600000 0 0
*[ default_freq 0]
xbar.ape 0 0 25500000 9600000 0 0
*[ default_freq 0]
adsp.ape 0 0 25500000 9600000 0 0
*[ default_freq 0]
adma.ape 0 0 25500000 9600000 0 0
*[ default_freq 0]
aclk_slcg_ovr 0 0 25500000 9600000 0 0
*[ default_freq 0]
ape_slcg_ovr 0 0 25500000 9600000 0 0
*[ default_freq 0]
sata_oob 0 0 204000000 204000000 0 0
*[ default_freq 0]
sata 0 0 102000000 104000000 0 0
*[ default_freq 0]
sata_slcg_ovr_fpci 0 0 102000000 19200000 0 0
*[ default_freq 0]
sata_slcg_ovr_ipfs 0 0 102000000 19200000 0 0
*[ default_freq 0]
sata_slcg_ovr 0 0 102000000 19200000 0 0
*[ default_freq 0]
sbc4 1 1 12000000 12000000 0 0
*[ default_freq 0]
dfll_ref 2 2 51000000 51000000 0 0
*[ default_freq 0]
dfll_soc 2 2 51000000 51000000 0 0
*[ default_freq 0]
sclk_mux 2 2 408000000 204000000 0 0
*[ default_freq 0]
sclk 2 2 204000000 204000000 0 0
*[ default_freq 0]
sclk_skipper 2 2 204000000 408000000 0 0
*[ default_freq 0]
sbus 2 2 204000000 204000000 0 0
*[ default_freq 0]
vcm.sclk 0 0 204000000 204000000 0 0
*[ default_freq 0]
cap.vcore.sclk 0 0 408000000 4294967295 0 0
*[ default_freq 0]
camera.sclk 0 0 204000000 204000000 0 0
*[ default_freq 0]
mon.avp 0 0 204000000 204000000 0 0
*[ default_freq 0]
wake.sclk 0 0 204000000 204000000 0 0
*[ default_freq 0]
bsea.sclk 0 0 204000000 204000000 0 0
*[ default_freq 0]
avp.sclk 1 1 204000000 204000000 0 0
*[ default_freq 0]
override.sclk 0 0 204000000 204000000 0 0
*[ default_freq 0]
floor.sclk 0 0 204000000 204000000 0 0
*[ default_freq 0]
cap.throttle.sclk 0 0 408000000 408000000 0 0
*[ default_freq 0]
cap.sclk 0 0 408000000 408000000 0 0
*[ default_freq 0]
ahb.sclk 1 1 102000000 51000000 0 0
*[ default_freq 0]
sdmmc4.sclk 0 0 102000000 204000000 0 0
*[ default_freq 0]
vcm.ahb.sclk 0 0 102000000 204000000 0 0
*[ default_freq 0]
usb2.sclk 0 0 102000000 204000000 0 0
*[ default_freq 0]
usb1.sclk 0 0 102000000 204000000 0 0
*[ default_freq 0]
usbd.sclk 0 0 102000000 204000000 0 0
*[ default_freq 0]
apb.sclk 1 1 51000000 51000000 0 0
*[ default_freq 0]
wifi.sclk 0 0 51000000 132800000 0 0
*[ default_freq 0]
vcm.apb.sclk 0 0 51000000 102000000 0 0
*[ default_freq 0]
boot.apb.sclk 1 1 51000000 51000000 0 0
*[ default_freq 0]
qspi.sclk 0 0 51000000 102000000 0 0
*[ default_freq 0]
sbc4.sclk 0 0 51000000 102000000 0 0
*[ default_freq 0]
sbc3.sclk 0 0 51000000 102000000 0 0
*[ default_freq 0]
sbc2.sclk 0 0 51000000 102000000 0 0
*[ default_freq 0]
sbc1.sclk 0 0 51000000 102000000 0 0
*[ default_freq 0]
hclk_div 1 1 102000000 204000000 0 0
*[ default_freq 0]
hclk 1 1 102000000 102000000 0 0
*[ default_freq 0]
pclk_div 1 1 51000000 102000000 0 0
*[ default_freq 0]
pclk 1 1 51000000 51000000 0 0
*[ default_freq 0]
cec 0 0 51000000 0 0 0
*[ default_freq 0]
uartd 0 0 408000000 408000000 0 0
*[ default_freq 0]
uartc 0 0 408000000 408000000 0 0
*[ default_freq 0]
uartb 0 0 408000000 408000000 0 0
*[ default_freq 0]
hda 1 1 51000000 51000000 0 0
*[ default_freq 0]
hda2codec_2x 1 1 48000000 48000000 0 0
*[ default_freq 0]
pll_p_out_adsp 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out_cpu 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out4_div 0 0 102000000 0 0 0
*[ default_freq 0]
pll_p_out4 0 0 102000000 102000000 0 0
*[ default_freq 0]
dpaux1 0 0 408000000 408000000 0 0
*[ default_freq 0]
uarta 1 1 408000000 408000000 0 0
*[ default_freq 0]
csite 1 1 136000000 136000000 0 0
*[ default_freq 0]
vi_sensor 0 0 408000000 408000000 0 0
*[ default_freq 0]
soc_therm 1 1 51000000 51000000 0 0
*[ default_freq 0]
vi_sensor2 0 0 408000000 408000000 0 0
*[ default_freq 0]
sdmmc1 0 0 6000000 6000000 0 0
*[ default_freq 0]
spdif_in 0 0 408000000 408000000 0 0
*[ default_freq 0]
mselect 1 1 102000000 102000000 0 0
*[ default_freq 0]
mselect_master 0 0 102000000 102000000 0 0
*[ default_freq 0]
override.mselect 0 0 102000000 102000000 0 0
*[ default_freq 0]
pcie.mselect 0 0 102000000 102000000 0 0
*[ default_freq 0]
cpu.mselect 0 0 102000000 102000000 0 0
*[ default_freq 0]
afi 0 0 102000000 102000000 0 0
*[ default_freq 0]
host1x 1 1 12000000 136000000 0 0
*[ default_freq 0]
host1x_master 0 0 12000000 12000000 0 0
*[ default_freq 0]
override.host1x 0 0 12000000 163200000 0 0
*[ default_freq 0]
floor.host1x 0 0 12000000 163200000 0 0
*[ default_freq 0]
cap.vcore.host1x 0 0 408000000 4294967295 0 0
*[ default_freq 0]
cap.host1x 0 0 408000000 408000000 0 0
*[ default_freq 0]
vii2c.host1x 0 0 12000000 163200000 0 0
*[ default_freq 0]
vi.host1x 0 0 12000000 163200000 0 0
*[ default_freq 0]
nv.host1x 0 0 12000000 81000000 0 0
*[ default_freq 0]
i2c5 1 2 136000000 136000000 0 0
*[ default_freq 0]
i2c3 0 1 81600000 83200000 0 0
*[ default_freq 0]
i2c2 1 1 81600000 83200000 0 0
*[ default_freq 0]
i2c1 1 1 81600000 83200000 0 0
*[ default_freq 0]
pll_p_out_hsio 1 1 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out_xusb 3 3 408000000 408000000 0 0
*[ default_freq 0]
xusb_dev_src 1 1 102000000 102000000 0 0
*[ default_freq 0]
xusb_dev 0 0 102000000 19200000 0 0
*[ default_freq 0]
xusb_dev_slcg_ovr 0 0 102000000 19200000 0 0
*[ default_freq 0]
xusb_host_src 1 1 102000000 102000000 0 0
*[ default_freq 0]
xusb_host 2 2 102000000 19200000 0 0
*[ default_freq 0]
xusb_host_slcg_ovr 0 0 102000000 19200000 0 0
*[ default_freq 0]
xusb_falcon_src 1 1 204000000 204000000 0 0
*[ default_freq 0]
pll_p_out5_div 0 0 204000000 408000000 0 0
*[ default_freq 0]
pll_p_out5 0 0 204000000 204000000 0 0
*[ default_freq 0]
pll_p_out3_div 0 0 102000000 408000000 0 0
*[ default_freq 0]
pll_p_out3 0 0 102000000 102000000 0 0
*[ default_freq 0]
csi 0 0 102000000 408000000 0 0
*[ default_freq 0]
sdmmc_legacy 0 0 102000000 408000000 0 0
*[ default_freq 0]
pll_p_out1_div 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out1 0 0 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out2 0 0 204000000 0 0 0
*[ default_freq 0]
pll_p_ud 0 0 408000000 0 0 0
*[ default_freq 0]
sor_safe 1 1 24000000 0 0 0
*[ default_freq 0]
sor1 0 0 24000000 0 0 0
*[ default_freq 0]
sor0 0 0 24000000 0 0 0
*[ default_freq 0]
pll_d2 0 0 594000000 594000000 0 0
*[ default_freq 0]
pll_d2_out0 0 0 594000000 768000000 0 0
*[ default_freq 0]
pll_dp 0 0 270000000 270000000 0 0
*[ default_freq 0]
pll_c4_vco 0 0 998400000 998400000 0 0
*[ default_freq 0]
pll_c4_out2 0 0 199680000 134400000 0 0
*[ default_freq 0]
sdmmc4 0 0 199680000 200000000 0 0
*[ default_freq 0]
pll_c4_out1 0 0 332800000 224000000 0 0
*[ default_freq 0]
pll_c4_out0 0 0 998400000 0 0 0
*[ default_freq 0]
pll_c4_out3_div 0 0 998400000 672000000 0 0
*[ default_freq 0]
pll_c4_out3 0 0 998400000 672000000 0 0
*[ default_freq 0]
pll_e 1 1 100000000 100000000 0 0
*[ default_freq 0]
cml1 0 0 100000000 100000000 0 0
*[ default_freq 0]
cml0 0 0 100000000 100000000 0 0
*[ default_freq 0]
pll_re_vco 1 1 672000000 672000000 0 0
*[ default_freq 0]
pll_re_out1_div 0 0 672000000 624000000 0 0
*[ default_freq 0]
pll_re_out1 0 0 672000000 624000000 0 0
*[ default_freq 0]
pll_re_out 0 0 672000000 624000000 0 0
*[ default_freq 0]
pll_d 0 0 326400000 326400000 0 0
*[ default_freq 0]
pll_d_out0 0 0 163200000 163200000 0 0
*[ default_freq 0]
pll_d_dsi_out 0 0 163200000 163200000 0 0
*[ default_freq 0]
dsib 0 0 163200000 163200000 0 0
*[ default_freq 0]
dsi 0 0 163200000 163200000 0 0
*[ default_freq 0]
pll_u_vco 2 2 480000000 480000000 0 0
*[ default_freq 0]
pll_u_480M 1 1 480000000 480000000 0 0
*[ default_freq 0]
xusb_ss_src 3 3 120000000 120000000 0 0
*[ default_freq 0]
xusb_ss 2 2 120000000 19200000 0 0
*[ default_freq 0]
xusb_ssp_src 1 1 120000000 19200000 0 0
*[ default_freq 0]
xusb_hs_src 2 2 120000000 19200000 0 0
*[ default_freq 0]
xusb_ss_div2 0 0 60000000 0 0 0
*[ default_freq 0]
pll_u_out 2 2 240000000 240000000 0 0
*[ default_freq 0]
pll_u_out2_div 1 1 60000000 240000000 0 0
*[ default_freq 0]
pll_u_out2 1 1 60000000 60000000 0 0
*[ default_freq 0]
pll_u_60M 0 0 60000000 240000000 0 0
*[ default_freq 0]
pll_u_out1_div 1 1 48000000 240000000 0 0
*[ default_freq 0]
pll_u_out1 2 2 48000000 48000000 0 0
*[ default_freq 0]
pll_u_48M 1 1 48000000 240000000 0 0
*[ default_freq 0]
xusb_fs_src 2 2 48000000 19200000 0 0
*[ default_freq 0]
pll_c3 0 0 192000000 192000000 0 0
*[ default_freq 0]
nvdec 0 0 192000000 192000000 0 0
*[ default_freq 0]
nvdec_slcg_ovr 0 0 192000000 408000000 0 0
*[ default_freq 0]
nvenc 0 0 192000000 408000000 0 0
*[ default_freq 0]
nvenc_slcg_ovr 0 0 192000000 408000000 0 0
*[ default_freq 0]
c3bus 0 0 192000000 0 0 0
*[ default_freq 0]
cap.vcore.c3bus 0 0 1200000000 4294967295 0 0
*[ default_freq 0]
floor.c3bus 0 0 192000000 307200000 0 0
*[ default_freq 0]
override.c3bus 0 0 192000000 307200000 0 0
*[ default_freq 0]
cap.throttle.c3bus 0 0 1200000000 1200000000 0 0
*[ default_freq 0]
cap.c3bus 0 0 1200000000 1200000000 0 0
*[ default_freq 0]
nvdec.cbus 0 0 192000000 0 0 0
*[ default_freq 0]
nvenc.cbus 0 0 192000000 1200000000 0 0
*[ default_freq 0]
pll_c2 0 0 140800000 140800000 0 0
*[ default_freq 0]
se 0 0 140800000 537600000 0 0
*[ default_freq 0]
tsecb 0 0 140800000 140800000 0 0
*[ default_freq 0]
nvjpg 0 0 140800000 408000000 0 0
*[ default_freq 0]
nvjpg_slcg_ovr 0 0 140800000 408000000 0 0
*[ default_freq 0]
vic03 0 0 140800000 140800000 0 0
*[ default_freq 0]
vic03_slcg_ovr 0 0 140800000 19200000 0 0
*[ default_freq 0]
c2bus 0 0 140800000 0 0 0
*[ default_freq 0]
vic.floor.cbus 0 0 140800000 0 0 0
*[ default_freq 0]
cap.vcore.c2bus 0 0 1200000000 4294967295 0 0
*[ default_freq 0]
edp.c2bus 0 0 1200000000 1200000000 0 0
*[ default_freq 0]
override.c2bus 0 0 140800000 307200000 0 0
*[ default_freq 0]
floor.c2bus 0 0 140800000 307200000 0 0
*[ default_freq 0]
cap.throttle.c2bus 0 0 1200000000 1200000000 0 0
*[ default_freq 0]
cap.c2bus 0 0 1200000000 1200000000 0 0
*[ default_freq 0]
tsecb.cbus 0 0 140800000 1200000000 0 0
*[ default_freq 0]
se.cbus 0 0 140800000 510000000 0 0
*[ default_freq 0]
nvjpg.cbus 0 0 140800000 1200000000 0 0
*[ default_freq 0]
vic03.cbus 0 0 140800000 140800000 0 0
*[ default_freq 0]
pll_c 0 0 217600000 217600000 0 0
*[ default_freq 0]
isp 0 0 217600000 408000000 0 0
*[ default_freq 0]
ispb 0 0 217600000 19200000 0 0
*[ default_freq 0]
ispb_slcg_ovr 0 0 217600000 19200000 0 0
*[ default_freq 0]
ispa 0 0 217600000 19200000 0 0
*[ default_freq 0]
ispa_slcg_ovr 0 0 217600000 19200000 0 0
*[ default_freq 0]
vi 0 0 217600000 408000000 0 0
*[ default_freq 0]
vi_slcg_ovr 0 0 217600000 408000000 0 0
*[ default_freq 0]
vi_output 0 0 217600000 0 0 0
*[ default_freq 0]
cbus 0 0 217600000 0 0 0
*[ default_freq 0]
override.cbus 0 0 217600000 307200000 0 0
*[ default_freq 0]
isp.cbus 0 0 217600000 307200000 0 0
*[ default_freq 0]
ispb.isp.cbus 0 0 217600000 1200000000 0 0
*[ default_freq 0]
ispa.isp.cbus 0 0 217600000 1200000000 0 0
*[ default_freq 0]
vi.cbus 0 0 217600000 307200000 0 0
*[ default_freq 0]
vi_bypass.cbus 0 0 217600000 307200000 0 0
*[ default_freq 0]
vi_v4l2.cbus 0 0 217600000 1200000000 0
How can I set the “clk_out_3” clock rate at Jetson TX1 reset?
hello sensor_test,
please add some debug prints in the kernel driver,
to check the clock frequency during property reading.
thanks
sources/kernel/kernel-4.4/drivers/media/platform/tegra/camera/sensor_common.c
79 err = read_property_u32(node, "mclk_khz", &value);
80 if (err)
81 signal->mclk_freq = 0;
82 else
83 signal->mclk_freq = value;
Hi sensor_test,
Did you find a fix for this ?
I get the exact same error, but my mlck reports as 2400000 as it should.
“ERROR: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Internal data flow error.”
and zero bytes in RAW data
The driver was working on “TX2” 28.2 pre release but as soon as i upgraded to 28.2 finale release i got this problem :/
and if try to capture video with nvcamerasrc the nvcamera_deamon crashes and hangs…
Only output from nccamerasrc is: Using winsys x11 and then nothing…
All was fine before 28.2 finale :)
I have the same problem … any fix for this ?
I’m using Jetson nano, and get this problem as well.