Hi, I am loading 32-bit float data from global to shared like this [pic] The shared memory is defined as a 16 x 8 row-major matrix. Each thread in a warp loads 4 floats from global and store to shared. Here shared memory banks repeat every 4 rows ie T0-T7 are accessing different banks. Basically…

[image] unital: I am abit struggling to understand what this means? The thing you have excerpted only applies to cc2.0 devices, which you can discover by carefully reading the thread you linked. The idea that 128-bit per thread accesses automatically give rise to bank conflicts is not applic…

Edited: Post deleted due to incorrect understanding.

[image] rs277: Threads 0-7 will be loading into banks 0-31, as will threads 8-15, 16-23 and 24-31, so a 4 way conflict. On a load involving 128 bits per thread, the load request will be split up by the GPU into 4 phases, what used to be called transactions. Those 4 phases are executed indepe…

The load is done in 4 phases because shared memory has a bandwidth of 32 bits per bank per cycle (ignoring certain kepler variants/situations). With a 128-bit load per thread, considered warp-wide, that is a total of 512 bytes being requested. Since shared memory can serve up only 128 bytes per cy…

Thanks alot @Robert_Crovella @rs277 for the clarification.

Can I ask one more thing? It looks like this kernel has a bottleneck at shared store with 95% long scoreboard. Looking at the profiling guide it states Warp was stalled waiting for a scoreboard dependency on a L1TEX (local, global, surface, texture) operation. Find the instruction producing the da…

[image] unital: I am assuming at this point data has loaded from global memory into register and somehow its taking alot of time for data in register to be stored into shared memory? That isn’t the right way to think about it. A clue for proper analysis is given in your excerpted text: […

Thanks so much @Robert_Crovella for the explanation. It really cleared up my confusion.

[image] Robert_Crovella: On a load involving 128 bits per thread, the load request will be split up by the GPU into 4 phases I have a question about this. Does the “phases” mean “wavefronts”?

128-bit access bank conflict

Accelerated Computing CUDA CUDA Programming and Performance

rs277 March 22, 2024, 6:36pm 5

Thanks, my understanding was that these phases were conflicts. I’ll amend my post.

So if the load is done in 4 phases, the performance impact will presumably be the same as for conflicts?

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128-bit access bank conflict

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