Looking at the mmap buffer dump log, it looks like one frame is missing regularly. Isn’t it related to CRC error?
The situation after that
Supported CRC error correction with sensor (FPGA).
This resolved the CRC error on the TX2, but the frame rate remained at 30fps.
From these surveys
We focused on the wait condition in the nvhost_syncpt_wait_timeout_ext function.
Here, there was an unknown wait, and I thought it was the cause.
The nvhost_syncpt_wait_timeout_ext function seems to detect certain hardware interrupts.
A hardware interrupt counts up SyncPT.
When the threshold is exceeded, it seems to be released from the waiting process.
How many interrupts are there to count SyncPT?
Also, I want to know which interrupt signal is.
Thank you for your advice.
What we know is that FE events are not in 16msec cycles.
The cycle remains unchanged at 30 msec.
How can I check the status of FE events?
Where didn’t you find Parker_SI_Errata_DA07897002v05 [7] .pdf
I have no idea to solve this problem now. Still consult with developer to find the root cause.
I would like to confirm that the cause may be that the time from FE to FS is too short.
Is the following log time stamp in nsec units?
tstamp: 14581547634
From the analysis result of the FS / FE event log
FS / FE has been generated, but CHANSEL_PXL_SOF has not been generated. In the system
Isn’t there a possibility that something is wrong with the CSIMUX block and CHANSEL block areas?
I have something to tell you.
Fixed the Vi driver to disable single shot mode.
This made it work at a frame rate of 60fps.
Is this correspondence correct?
I need your point of view.