A number of topics, listed below, have discussed glass to glass latency for TX1 and TX2. At this point, it seems that observed latency for the TX1 is less than for TX2. Several discussions noted that decreasing the buffer queue size decreases the latency. No discussion fully explains the observed latencies over the expected 2 or 3 frames for TX2, except possibly for the post in …1026587… by Nvidia.
Are there currently any full explanations for the observed latencies?
A current industrial application under development uses multiple CSI sensors with raw 10 bit monochrome output format at various frame sizes and frame rates of at least 60fps. The application requires single frame CSI to computational buffer latency.
The question is: Can the TX2 and V4l2 can be configured to support single frame CSI to buffer latency?
In attempting to measure latency, one would expect to be able to use the sof and eof event timers described in the Video Input chapter (27) of the Parker TRM. As post …1046381… discussed, it is not clear how the timestamps align with the real time clock. Nor is it clear which of the sof timestamps queued by the NOTIFY block is the one embedded in the captured buffer, nor is there any evident access to the other queued timestamps.
Following this approach yields an unrealistically low latency on taking the difference between the SOF time stamp embedded in the buffer and the value of TSC read when the buffer becomes available in user space.
Is there a means of accessing all of the timestamps captured by NOTIFY?
What alignment do these timestamps have to any other clock?
A related question.
Should CHANSEL_LOAD_FRAMED appear in an RTCPU trace of a normal frame, or does it indicate an error?
Specifically, does this flag indicate a premature (early) load command, executed before a frame ends?