Hi @ShaneCCC
We dump the two sensors, but their indexs are the same. We thought that there should be index0 and index1, refer to this post.
root@t-desktop:/home/t# v4l2-ctl -d /dev/video0 --list-formats-ext
ioctl: VIDIOC_ENUM_FMT
Index : 0
Type : Video Capture
Pixel Format: 'GREY'
Name : 8-bit Greyscale
Size: Discrete 640x400
Interval: Discrete 0.008s (120.000 fps)
root@t-desktop:/home/t#
root@t-desktop:/home/t# v4l2-ctl -d /dev/video1 --list-formats-ext
ioctl: VIDIOC_ENUM_FMT
Index : 0
Type : Video Capture
Pixel Format: 'GREY'
Name : 8-bit Greyscale
Size: Discrete 640x400
Interval: Discrete 0.008s (120.000 fps)
is the mapping right?
What’s more, how to debug CHANSEL_SHORT_FRAME promble, we have been trapped in it.
update Dynamic debug log
[ 838.458148] ov9281 2-0010: ov9281_s_stream: write mode table 3
[ 838.477876] ov9281 2-0010: ov9281_s_stream: write fsync table 2
[ 838.552777] ov9281 2-0010: ov9281_s_stream: write fsync slave mode table 3
[ 838.560385] ov9281 2-0010: ov9281_s_stream: stream on
[ 838.578577] video4linux video1: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc17b2af800]
[ 838.779593] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 838.786418] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 838.796677] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[ 838.796689] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 838.796702] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000200
[ 838.796716] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 838.796736] nvcsi 150c0000.nvcsi: csi4_cil_check_status 407
[ 838.796745] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x0000000e
[ 838.804854] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x0000000e
[ 838.813249] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[ 838.813253] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 838.813264] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 838.813273] nvcsi 150c0000.nvcsi: csi4_stream_config (1) read VC0_DPCM_CTRL = 00000000
[ 838.813277] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 838.813282] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 838.813290] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 200
[ 838.813294] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 838.813297] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 22
[ 838.813577] tegra-vi4 15700000.vi: Create Surface with imgW=640, imgH=400, memFmt=16
[ 838.813588] video4linux video1: free_ring_buffers: capture init latency is 370 ms
[ 838.820509] video4linux video1: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc17b2ad000]
[ 839.023620] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 839.030209] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 839.040141] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[ 839.040148] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 839.040156] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000200
[ 839.040165] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 839.040180] nvcsi 150c0000.nvcsi: csi4_cil_check_status 407
[ 839.040186] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x0000000e
[ 839.048240] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x0000000e
[ 839.056621] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[ 839.056624] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 839.056638] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 839.056648] nvcsi 150c0000.nvcsi: csi4_stream_config (1) read VC0_DPCM_CTRL = 00000000
[ 839.056651] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 839.056656] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 839.056664] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 200
[ 839.056667] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 839.056670] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 22
[ 839.056941] tegra-vi4 15700000.vi: Create Surface with imgW=640, imgH=400, memFmt=16
[ 839.062509] video4linux video1: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc17b2af800]
[ 839.263583] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 839.270240] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 839.281008] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[ 839.281020] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 839.281031] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000200
[ 839.281043] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 839.281061] nvcsi 150c0000.nvcsi: csi4_cil_check_status 407
[ 839.281069] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x0000000e
[ 839.289177] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x0000000e
[ 839.297642] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[ 839.297647] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 839.297661] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 839.297672] nvcsi 150c0000.nvcsi: csi4_stream_config (1) read VC0_DPCM_CTRL = 00000000
[ 839.297676] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 839.297684] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 839.297693] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 200
[ 839.297698] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 839.297701] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 22
[ 839.298032] tegra-vi4 15700000.vi: Create Surface with imgW=640, imgH=400, memFmt=16
[ 839.304509] video4linux video1: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc17b2ad000]
[ 839.507555] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 839.514208] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 839.525307] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2
[ 839.525342] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 839.525367] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000200
[ 839.525391] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 839.525424] nvcsi 150c0000.nvcsi: csi4_cil_check_status 407
[ 839.525443] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_INTR_STATUS 0x0000000e
[ 839.533605] nvcsi 150c0000.nvcsi: csi4_cil_check_status (1) CILA_ERR_INTR_STATUS 0x0000000e
[ 839.542002] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=2
[ 839.542009] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 839.542026] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 839.542036] nvcsi 150c0000.nvcsi: csi4_stream_config (1) read VC0_DPCM_CTRL = 00000000
[ 839.542041] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 839.542049] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 839.542058] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 200
[ 839.542064] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 839.542069] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 22
[ 839.542412] tegra-vi4 15700000.vi: Create Surface with imgW=640, imgH=400, memFmt=16
[ 839.546524] video4linux video1: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc17b2af800]
[ 839.747644] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 839.754316] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 839.765475] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=2