it should be okay, I assume you’re using the same gst pipeline to capture 1.5G stream.
let’s try to gather VI tracing logs with clocks boosted,
and, using below v4l2 standard IOCTL to fetch the camera stream,
for instance, $ v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1536,pixelformat=UYVY --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100
it looks there’s no validate frames detected by VI engine,
let me share VI tracing logs with a success image capture as an example,
here must be one pair of CHANSEL_PXL_SOF/CHANSEL_PXL_EOF to indicate a frame has detected by VI engine.
afterwards, it’s ATOMP_FRAME_DONE to indicate it’s complete writing a frame to memory.
for instance,
did you double check you’ve loading device tree settings correctly?
please execute below commands to dump device tree into dts formats for checking.
for instance, $ sudo dtc -I fs -O dts /sys/firmware/devicetree/base > /tmp/123.dts
有个疑问,
Skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.
An initiation deskew signal should be sent by sensor or deserializer to perform the skew calibration. If the deskew signals is not sent, the receiver will stall, and the capture will time out.
You can calculate the output data rate with the following equation:
Output data rate = (sensor or deserializer pixel clock in hertz) * (bits per pixel) / (number of CSI lanes)
这里说,如果output data rate大于1.5Gbps,需要Skew calibration
1,
serdes_pix_clk_hz=500000000
max96724 Dphy data rate/lane=2.0G
这种情况是否需要Skew calibration
2,csi.c 的deskew_setup 里面
if (sig_props->serdes_pixel_clock.val != 0ULL)
pix_clk_hz = sig_props->serdes_pixel_clock.val;
else
pix_clk_hz = sig_props->pixel_clock.val;
deskew_enable = sig_props->deskew_initial_enable;
deskew calibration is a must if data-rate > 1.5 Gbps, Else the camera firmware will continue to wait for deskew signal from the sensor side. it’ll enable pixel parser when deskew calibration has completed.
this is due to DPHY deskew calibration not complete, it happened when the calibration sequence length is not long enough.
please give it a try to configure cil_settletime, and please also review the serdes_pix_clk_hz settings.
camera stack parse both of them, once you’ve serdes_pix_clk_hz, it should be larger than pix_clk_hz,
you may dig into below for details.
for instance, $public_sources/kernel_src/kernel/nvidia-oot/drivers/media/platform/tegra/camera/sensor_common.c
static int sensor_common_parse_signal_props{
...
if (signal->serdes_pixel_clock.val != 0ULL) {
if (signal->serdes_pixel_clock.val < signal->pixel_clock.val) {
dev_err(dev,
"%s: serdes_pix_clk_hz is lower than pix_clk_hz!\n",
__func__);
return -EINVAL;
}
rate = signal->serdes_pixel_clock.val;
...