Audio pins config on R32.2

Hi,
I want to config these pins for audio funtion:
AUDIO_MCLK --> GPIO BB.00
DAP4_SCLK --> GPIO J.07
DAP4_FS --> GPIO J.04
DAP4_DIN --> GPIO J.05
DAP4_DOUT --> GPIO J.06

on L4T R32.1, I can modify “tegra210-porg-super-module-e2614.dtsi”

--- a/sources/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-super-module-e2614.dtsi
+++ b/sources/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-super-module-e2614.dtsi
@@ -28,7 +28,7 @@
                                >;
                        label = "I2S4_LRCLK", "I2S4_SDIN", "I2S4_SDOUT",
                                "I2S4_CLK", "AUDIO_MCLK", "AUD_RST";
-                       status = "disabled";
+                       status = "okay";
                };
        };

then these pin are sfio.

$ sudo grep "Name:\|J:\|BB:" /sys/kernel/debug/tegra_gpio
[sudo] password for nvidia:
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 J: 2:1 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000

on L4T R32.2, I do the same thing. But these pins are still gpio.

$ sudo grep "Name:\|J:\|BB:" /sys/kernel/debug/tegra_gpio
[sudo] password for nvidia:
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 J: 2:1 f0 00 00 00 00 00 000000
BB: 6:3 01 00 00 00 00 00 000000

How can I config these pins on L4T R32.2?
Thanks!

Hello!

There is an application note for Jetson Nano that describes the process for updating the default pinmux settings for the 40-pin header on Jetson Nano [0]. Please note that in the current application note that there are a couple items that need to be corrected and will be corrected soon. These are …

  1. Step 4 on page 3 has a typo in the command where the command includes ‘p3450-port’ instead of ‘p3450-porg’
$ ./board-to-uboot.py p3450-porg > pinmux-config-p3450-porg.h
  1. If you are using L4T r32.1 (which you are not), then there is a build error that people have encountered when rebuilding the device-tree image [1]. If is not an issue for L4T r32.2 but we will update the application note to describe how to workaround this.

The process is a bit cumbersome and we are looking to improve this.

Regards,
Jon

[0] https://developer.nvidia.com/embedded/dlc/Jetson-Nano-40-Pin-Expansion-Header
[1] https://devtalk.nvidia.com/default/topic/1055398/jetson-nano/how-to-use-the-jetson-nanos-pinmux-spreadsheet-/post/5360003/#5360003

Hi jonathanh,
It works!
This is what I modified the u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h

diff --git a/sources/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h b/sources/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
index 49df131..a3b149b 100644
--- a/sources/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
+++ b/sources/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
@@ -52,10 +52,6 @@ static const struct tegra_gpio_config p3450_porg_gpio_inits[] = {
        GPIO_INIT(I,    0,   OUT0),
        GPIO_INIT(I,    1,   OUT1),
        GPIO_INIT(I,    2,   OUT0),
-       GPIO_INIT(J,    4,   IN),
-       GPIO_INIT(J,    5,   IN),
-       GPIO_INIT(J,    6,   IN),
-       GPIO_INIT(J,    7,   IN),
        GPIO_INIT(S,    5,   IN),
        GPIO_INIT(S,    7,   OUT0),
        GPIO_INIT(T,    0,   OUT0),
@@ -70,7 +66,6 @@ static const struct tegra_gpio_config p3450_porg_gpio_inits[] = {
        GPIO_INIT(Z,    0,   IN),
        GPIO_INIT(Z,    2,   IN),
        GPIO_INIT(Z,    3,   OUT0),
-       GPIO_INIT(BB,   0,   IN),
        GPIO_INIT(CC,   4,   IN),
        GPIO_INIT(CC,   7,   OUT1),
        GPIO_INIT(DD,   0,   IN),
@@ -148,6 +143,10 @@ static const struct pmux_pingrp_config p3450_porg_pingrps[] = {
        PINCFG(GEN1_I2C_SCL_PJ1,     I2C1,       NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
        PINCFG(GEN2_I2C_SCL_PJ2,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
        PINCFG(GEN2_I2C_SDA_PJ3,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
+       PINCFG(DAP4_FS_PJ4,          I2S4B,      DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DAP4_DIN_PJ5,         I2S4B,      DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DAP4_DOUT_PJ6,        I2S4B,      DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(DAP4_SCLK_PJ7,        I2S4B,      DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
        PINCFG(PK0,                  RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
        PINCFG(PK1,                  RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
        PINCFG(PK2,                  RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
@@ -216,7 +215,7 @@ static const struct pmux_pingrp_config p3450_porg_pingrps[] = {
        PINCFG(DAP2_SCLK_PAA1,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
        PINCFG(DAP2_DIN_PAA2,        I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
        PINCFG(DAP2_DOUT_PAA3,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-       PINCFG(AUD_MCLK_PBB0,        DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(AUD_MCLK_PBB0,        AUD,        UP,     NORMAL,   OUTPUT,  DISABLE, DEFAULT),
        PINCFG(DVFS_PWM_PBB1,        CLDVFS,     NORMAL, TRISTATE, OUTPUT,  DISABLE, DEFAULT),
        PINCFG(DVFS_CLK_PBB2,        RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
        PINCFG(GPIO_X1_AUD_PBB3,     RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),

But I still have a question,
why I have to set the gpio/sfio in u-boot on R32.2?
Setting in kernel dts doesn’t rewrite the setting in u-boot?

Thanks!

Hello!

The U-Boot bootloader strips the ‘pinctrl-names’ property for the Tegra pinmux device from the DTB so that the kernel will not attempt to reconfigure the pins on boot. The reason for this is because we only recommend setting the pin configuration once during boot as it could be possible for glitches to be seen on the pins as their state is configured. In most cases it is only necessary to configure the pins once, so for production systems we recommend that the pin confguration is set once during early boot. That said, for pins exposed on the 40-pin header we are evaluating whether we can relax that requirement for developers.

Regards,
Jon

Hello!

I also wanted to let you know that with JetPack 4.3 (L4T 32.3.1) and we now have a tool included to assist with the reconfiguration of the pins exposed by the 40-pin header so that you no longer need to rebuild and reflash. Please see the following:

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fhw_setup_jetson_io.html%23

Regards,
Jon

Hello!

Just to let you know that we have identified an issue with the Jetson.IO tool on Nano when updating Nano using SD card image. However, there is a simple fix availabe. Details are here:

https://devtalk.nvidia.com/default/topic/1068583/jetson-nano/jetpack-4-3-l4t-r32-3-1-released/post/5413341/#5413341

Regards,
Jon