Cache model and replacement policies for GPU memory

[iamkaka]

Hi, Is there anyone who know the cache model and their replacement polices for off-chip and on-chip memory in gpu?

L2 Cache: Set-associative ? LRU?
L1 Cache :Set-associative ? LRU?
Texture L1:Set-associative ? LRU?
Constant L1 cache:Set-associative ? LRU?

[iamkaka]

My current approach is to develope micro-benchmark to reveal such details.

I am also looking for the answer. set-associativity and replacement policies especially for the Maxwell architecture.

[allanmac]

The site hgpu.org is always a good place to check:

Dissecting GPU Memory Hierarchy through Microbenchmarking

Memory access efficiency is a key factor in fully utilizing the computational power of graphics processing units (GPUs). However, many details of the GPU memory hierarchy are not released by GPU vendors. In this paper, we propose a novel fine-grained microbenchmarking approach and apply it to three generations of NVIDIA GPUs, namely Fermi, Kepler and Maxwell, to expose the previously unknown characteristics of their memory hierarchies. Specifically, we investigate the structures of different GPU cache systems, such as the data cache, the texture cache and the translation look-aside buffer (TLB). We also investigate the throughput and access latency of GPU global memory and shared memory. Our microbenchmark results offer a better understanding of the mysterious GPU memory hierarchy, which will facilitate the software optimization and modelling of GPU architectures. To the best of our knowledge, this is the first study to reveal the cache properties of Kepler and Maxwell GPUs, and the superiority of Maxwell in shared memory performance under bank conflict.

[BulatZiganshin]

thank you, it’s a lot of information for me. unfortunately, searching for gpu internals is like digging for a gold :)

[gpu_l2_cache]

You are miss leading the community!

It is totally wrong! L2 cache is on-chip!! please get a clear definition of on-chip and off-chip!!

and the results in the paper https://arxiv.org/abs/1509.02308 are totally wrong!

Dissecting GPU Memory Hierarchy through Microbenchmarking

Memory access efficiency is a key factor in fully utilizing the computational power of graphics processing units (GPUs). However, many details of the GPU memory hierarchy are not released by GPU vendors. In this paper, we propose a novel fine-grained microbenchmarking approach and apply it to three generations of NVIDIA GPUs, namely Fermi, Kepler and Maxwell, to expose the previously unknown characteristics of their memory hierarchies. Specifically, we investigate the structures of different GPU cache systems, such as the data cache, the texture cache and the translation look-aside buffer (TLB). We also investigate the throughput and access latency of GPU global memory and shared memory. Our microbenchmark results offer a better understanding of the mysterious GPU memory hierarchy, which will facilitate the software optimization and modelling of GPU architectures. To the best of our knowledge, this is the first study to reveal the cache properties of Kepler and Maxwell GPUs, and the superiority of Maxwell in shared memory performance under bank conflict.

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