Calculating/Getting register adresses of gpio pins

[jost38]

Hi,
so I have worked through the TRM.
This is the way I found of calculating the correct registers:

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PIN 7 on Orin AGX

Find the Pin in the Pinmux excel sheet through Signalname from DevKitCarrierBoardSpecification
→ PIN7 MCLK05 L57 (Carrier Board Speci)
=> L57 MCLK05 SOC_GPIO33 GPIO3_PQ.06 (Excel Pinmux)

PADCTL:

1. search for “SOC_GPIO33” in TRM
   ->found in SystemCPomponents->MultipurposeIO->G3 Pad Control Registers
   :PADCTL_G3_SOC_GPIO33_0
   :Offset: 0x70
   :And Bit Description

2. Find Base adress Block
   From Table 8.4.1.6 Pad Control Grouping find corresponding Base Address Block
   ->G3 Yes PADCTL_A0

3. FInd Base Adress
   In Table 3.2.2 System Adress Map
   ->PADCTL_A0 0x02430000 0x02430fff SYSTEM

4. Combine Base and Offset
   0x02430000 + 0x70 = 0x02430070

5. Bit description
   12 E_SCHMT 0=Disable 1=Enable
   10 GPIO_SF_SEL 0=GPIO 1=SFIO
   8 E_LPDR 0=Disable 1=Enable
   7 E_LPBK 0=Disable 1=Enable
   6 E_INPUT 0=Disable 1=Enable
   5 E_IO_HV 0=Disable 1=Enable
   4 TRISTATE 0=Disable 1=Enable
   3:2 PUPD 0=None 1=PullDown 2=PullUp 3=RSVD
   1:0 PM 0=RSVD0 1=EXTPERIPH4 2=DCB 3=RSVD3

6. Usage
   Set GPIO: Bit 10 = 0.
   For the output, set Bit 4 = 0 ; Bit 6 = 0.
   For Input, set Bit 4 = 1 ; Bit 6 = 1.

GPIO Control Register

1. Identify GPIO Port and Number
   Port:Q Pin:6

2. Find corresponding GPIO controller
   ->From Table in Chapter 8.5.1.2 Features GPIO Controllers and Port Mapping
   GPIO_CTL2 M (8) N (8) EDP VDDIO_EDP
   P (8) Q (8) R (6) G3

3. Find Base Adress of controller
   ->In
   GPIO_CTL2_GPIO0 0x02230000 0x02230fff SYSTEM

=>IS GPIO_CTL2_GPIO0 CORRECT HERE AND WHY GPIO0 ?

4. Find Adresses of the Registers with Port(q) and Pin(6)
   ->In 8.5.6 GPIO Control Registers

GPIO_Q_ENABLE_CONFIG_06_0 Offset: 0x126c0
GPIO_Q_DEBOUNCE_THRESHOLD_06_0 Offset: 0x126c4
GPIO_Q_INPUT_06_0 Offset: 0x126c8
GPIO_Q_OUTPUT_CONTROL_06_0 Offset: 0x126cc
GPIO_Q_OUTPUT_VALUE_06_0 Offset: 0x126d0
GPIO_Q_INTERRUPT_CLEAR_06_0 Offset: 0x126d4
(GPIO_Q_INTERRUPT_STATUS_G6_0 Offset: 0x12718)

=> as seen the other Offsets als always constant from the first and a fixed value can be added

5. Combine Base and Offset Address
   0x02230000 + 0x126c0 = 0x022426c0 for ENABLE_CONFIG of pin pq.06 ?

6. Bit description
   ENABLE_CONFIG:
   7 TIMESTAMPING_FUNCTION 0=Disable 1=Enable
   6 INTERRUPT_FUNCTION 0=Disable 1=Enable
   5 DEBOUNCE_FUNCTION 0=Disable 1=Enable
   4 TRIGGER_LEVEL When NO TRIGGER: this field is irrelevant
   When LEVEL: 0 = Trigger on level Low. 1 = Trigger on Level High
   When SINGLE EDGE: 0 = Trigger on Falling Edge. 1 = Trigger on Raising Edge
   When BOTH EDGES: this field is irrelevant
   3:2 TRIGGER_TYPE 0=NO_TRIGGER 1=LEVEL 2=SINGLE_EDGE 3=DOUBLE_EDGE
   1 IN_OUT 0=In 1=Out
   0 GPIO_ENABLE 0=Disable 1=Enable

   DEBOUNCE_THRESHOLD:
   7:0 DEBOUNCE_THRESHOLD 0=No Debounce 1~N-1=Debouncing interval of 1 msec to (N-1) msec.

   INPUT:
   0 GPIO_IN This field holds the GPIO Input value sampled after the specified Debouncing interval

   OUTPUT_CONTROL:
   0 GPIO_OUT_CONTROL 0=DRIVEN 1=FLOATED

   OUTPUT_VALUE:
   0 GPIO_OUT_VAL This field holds the GPIO output value to be driven

   INTERRUPT_CLEAR
   0 GPIO_INTERRUPT_CLEAR 0=DON’T CLEAR 1=CLEAR.

   (INTERRUPT_STATUS:)
   (7:0 GPIO_INTERRUPT_STATUS 0=Interrupt not set 1=Interrupt set)

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However, I am unsure as to which the correct Base address of the GPIO controller would be.
Is it GPIO_CTL2_GPIO0 and why is it the one with the zero at the end?
Are the adresses for the pin pq.06 correct?
PADCTL = 0x02430070
GPIO_CTL = 0x022426c0 (for enable config)
This is regarding the Jetson Orin AGX.

For the Jetson Xavier Nx I’m unable to locate the System Address Map for the GPIO controller in the Xavier NX TRM.
With is present in the Orin Series TRM in Chapter 8.5.3.1 System Address Map (AMAP).
Can you also assist me in locating that for the jetson Xavier series.