Hello,
I am currently using a Jetson AGX Orin devkit with Jetpack 5.1.
At the moment, I control the GPIO Pins of the 40Pin header on the Devkit through the sysfiles with the GPIO numbers.
But I would like to be able to modify the Pin behavior directly through their register addresses.
Which I previously did on a Jetson Xavier NX, but I’m having trouble getting the addresses of the pins.
Before, I converted the default dtsi files via the “pinmux-dts2cfg.py” script to a cfg file.
In this, I could just read the register addresses for each pin and its control register.
pinmux.0x022138e0 = 0x00000001; # CONFIG T7
pinmux.0x02431070 = 0x00000000; # GPIO dap5_din_pt7
(Without actually using/flashing the config)
However, it seems converting dtsi files on AGX Orin is no longer possible/necessary. In Orin pinmux python giving key error Python pinmux-dts2cfg.py Error Processing GPIO File
For now I’m just using the Devkit and wish to control the Gpio-Pins on the 40Pin Header directly though their register address, for a lower and more consistent latency.
The linked article has basically the same information as the one I linked.
And I can’t find a way there to get the register address of the value for the gpio pin.
Is there anywhere the registers are stored, like they were in the now obsolete cfg file generated by the python script. Where I could cat for the specific gpio I’m looking for.
Or at least a way to calculate the address similar to the cfg register address of the pin.
Hi,
so I have worked through the TRM.
This is the way I found of calculating the correct registers:
PIN 7 on Orin AGX
Find the Pin in the Pinmux excel sheet through Signalname from DevKitCarrierBoardSpecification
→ PIN7 MCLK05 L57 (Carrier Board Speci)
=> L57 MCLK05 SOC_GPIO33 GPIO3_PQ.06 (Excel Pinmux)
PADCTL:
search for “SOC_GPIO33” in TRM
->found in SystemCPomponents->MultipurposeIO->G3 Pad Control Registers
:PADCTL_G3_SOC_GPIO33_0
:Offset: 0x70
:And Bit Description
Find Base adress Block
From Table 8.4.1.6 Pad Control Grouping find corresponding Base Address Block
->G3 Yes PADCTL_A0
FInd Base Adress
In Table 3.2.2 System Adress Map
->PADCTL_A0 0x02430000 0x02430fff SYSTEM
Combine Base and Offset
0x02430000 + 0x70 = 0x02430070
Usage
Set GPIO: Bit 10 = 0.
For the output, set Bit 4 = 0 ; Bit 6 = 0.
For Input, set Bit 4 = 1 ; Bit 6 = 1.
GPIO Control Register
Identify GPIO Port and Number
Port:Q Pin:6
Find corresponding GPIO controller
->From Table in Chapter 8.5.1.2 Features GPIO Controllers and Port Mapping
GPIO_CTL2 M (8) N (8) EDP VDDIO_EDP
P (8) Q (8) R (6) G3
Find Base Adress of controller
->In
GPIO_CTL2_GPIO0 0x02230000 0x02230fff SYSTEM
=>IS GPIO_CTL2_GPIO0 CORRECT HERE AND WHY GPIO0 ?
Find Adresses of the Registers with Port(q) and Pin(6)
->In 8.5.6 GPIO Control Registers
=> as seen the other Offsets als always constant from the first and a fixed value can be added
Combine Base and Offset Address
0x02230000 + 0x126c0 = 0x022426c0 for ENABLE_CONFIG of pin pq.06 ?
Bit description
ENABLE_CONFIG:
7 TIMESTAMPING_FUNCTION 0=Disable 1=Enable
6 INTERRUPT_FUNCTION 0=Disable 1=Enable
5 DEBOUNCE_FUNCTION 0=Disable 1=Enable
4 TRIGGER_LEVEL When NO TRIGGER: this field is irrelevant
When LEVEL: 0 = Trigger on level Low. 1 = Trigger on Level High
When SINGLE EDGE: 0 = Trigger on Falling Edge. 1 = Trigger on Raising Edge
When BOTH EDGES: this field is irrelevant
3:2 TRIGGER_TYPE 0=NO_TRIGGER 1=LEVEL 2=SINGLE_EDGE 3=DOUBLE_EDGE
1 IN_OUT 0=In 1=Out
0 GPIO_ENABLE 0=Disable 1=Enable
DEBOUNCE_THRESHOLD:
7:0 DEBOUNCE_THRESHOLD 0=No Debounce 1~N-1=Debouncing interval of 1 msec to (N-1) msec.
INPUT:
0 GPIO_IN This field holds the GPIO Input value sampled after the specified Debouncing interval
(INTERRUPT_STATUS:)
(7:0 GPIO_INTERRUPT_STATUS 0=Interrupt not set 1=Interrupt set)
However, I am unsure as to which the correct Base address of the GPIO controller would be.
Is it GPIO_CTL2_GPIO0 and why is it the one with the zero at the end?
Are the adresses for the pin pq.06 correct?
PADCTL = 0x02430070
GPIO_CTL = 0x022426c0 (for enable config)
This is regarding the Jetson Orin AGX.
For the Jetson Xavier Nx I’m unable to locate the System Address Map for the GPIO controller in the Xavier NX TRM.
With is present in the Orin Series TRM in Chapter 8.5.3.1 System Address Map (AMAP).
Can you also assist me in locating that for the jetson Xavier series.
Thank you for the confirmation.
Can you still explain why GPIO_CTL2_GPIOzero is the correct base address?
Respectively if it is always GPIO_CTLx_GPIO0 (GPIOzero) and what the other GPIO_CTLx_GPIOy meaning/purpose is.
I just realized that PIN16 of the 40Pin expansion header is part of the AON Group, with it being GPIO3_PBB.0.
And for them the TRM mentions:
All AON, i.e. GPIO_, Control Registers share the same base address under the name AON_GPIO_0,
where = AA, BB, CC, DD, EE, and GG.
Basically the same as for the Non AON Control Registers.
However, I am unable to find the base Address of the AON GPIO Control Register (AON_GPIO_0) in the Address Map of the TRM, as mentioned right below:
For the base address of Non-AON GPIO Control Registers (GPIO_CTL) and AON GPIO Control Registers (AON_GPIO_0), please refer to the System Address Map in this TRM.
As there seems to no AON_GPIO_0 mentioned in the System Address map.
But I found in a git repo (jetGpio) the base Address of AON_GPIO_0 to be 0x0c2f0000.
Which worked for reading the values of a pin when added with its offset.
But I am not able to find that information in the TRM.
