Accessing problem to GPIO register of Xavier NX

Robotics & Edge Computing Jetson & Embedded Systems Jetson Xavier NX
1

Hello, i am trying to find Xavier NX 40 pin GPIO register address in the Xavier Series SoC Technical Reference Manual .

Before that i was using Jetson Nano 2GB Developer Kit and i was reaching to the 40 Pin GPIO Address via Direct Register Access. So i can not find GPIO register Address Map for Jetson Xavier NX developer Kit 40 Pin GPIO’s. Here is the image of Jetson Nano GPIO Register Address Map Table which i need for Xavier NX Developer Kit.

gpio_register_address_map
gpio_register_address_map696×257 44.8 KB

Is there any table for Jetson Xavier NX developer Kit like this?
Could you please help me out?

1 Like
3

hello i.ucurmak,

you may check with below to find out the reg address.
i.e. # cat /sys/kernel/debug/tegra_pinctrl_reg

please refer to below for an example to check GPIO3_PQ.03

# cat tegra_pinctrl_reg | grep pq3
Bank: 0 Reg: 0x02430068 Val: 0x00000058 -> soc_gpio23_pq3
4

Thanks JerryChang,
Now i can reach the register addresses of each pins, but still there is a problem with configuring to the pins.

For example when i want to reach gpio pin 19 which is on 40 pin header, it’s state does not change.
I am using sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep pz5 command for getting register address of pin 19. This is register address of pin 19 Bank: 0 Reg: 0x0243d058 Val: 0x0000005f → spi1_mosi_pz5.

Firstly i also need to know Controller register adresses, i.e. GPIO3_PQ controller register address. Because when i configure the pins, i also configure the their controller. You can see my configuration code below. (This configuration works for Jetson Nano 2GB.)
In the code pin[0] is the controller register address and pin[1] is the pin bit value. i.e GPIO3_PQ.03 ; pin[1] value 0x08 and pin[0] value should be GPIO3_PQ controller register address which i need to know.

// read physical memory
int fd = open(“/dev/mem”, O_RDWR | O_SYNC);

// map a particular physical address into our address space
int pagesize = getpagesize();
int pagemask = pagesize-1;

// This page will actually contain all the GPIO controllers, because they are co-located
void *base = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd, (pin[0] & ~pagemask));
if (base == NULL) {
perror(“mmap()”);
exit(1);
}

// set up a pointer for convenient access – this pointer is to the selected GPIO controller
gpio_t volatile *pinRelay = (gpio_t volatile *)((char *)base + (pin[0] & pagemask));
// Chose a pin from controller
pinRelay->CNF |= pin[1];

// Enable output
pinRelay->OE = OUTPUT;

// Disable interrupts
pinRelay->INT_ENB = 0x00;

5

please also check Jetson Xavier NX Pinmux Table for the default pin configurations.

6

I already checked, but i can’t see any useful information about my problem. Is the configuration code same as
Jetson nano? I need to access to Controllers physical address via Direct Memory Access method. Thus is there any other way to find out those physical addresses via TRM?

7

hello i.ucurmak,

we usually control GPIO via kernel interface, you may check GPIO Changes session to check the GPIO number, toggle it through sysfs.
note, you should also check the GPIO header file, tegra194-gpio.h for the Xavier series .
for example,
$L4T_Sources/r32.5/Linux_for_Tegra/source/public/kernel/nvidia/include/dt-bindings/gpio/tegra194-gpio.h

8

Hi.
I am not using virtual memory, because i have a project to do via direct register access. But i want to do my job in user space not in kernel space.
I have modified this repository for my own purposes, i am directly accessing all of the gpio pins on nano via DMA from user space.

There is an solved issue for Jetson Nano 2 GB developer kit. So, i need similar solution for Jetson Xavier NX Developer Kit. I can not use this solution for Xavier NX because, i do not have Xavier NX Developer Kit Pinmux Table. I only found Xavier NX Module Pinmux.

solved_issue_for_nano
solved_issue_for_nano1423×538 70.2 KB

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10

hello i.ucurmak,
Firstly, Nano is on different tegra chip while Xavier is on different so GPIO address mapping also differs very much.
Z6 controller address will not be same as Z4 or any other Z port. All have separate addresses unlike Nano.
You can get GPIO address from pinmux BCT file. For pz5, search for “CONFIG Z5”
pinmux.0x022124a0 = 0x00000001; # CONFIG Z5
Here: 0x022124a0 is the GPIO address.
Bit 0 : GPIO_ENABLE (if set to 1 means pin is GPIO)
Bit 1: IN_OUT (if 1 : OUT, 0: IN)
For more details: you can also refer gpio-tegra186.c kernel driver present in our kernel source code.
You can get reg offset from #define TEGRA_MAIN_GPIO_PORT_INFO(port, cid, cind, npins) and there are other structures present.

Thanks,
Shubhi

1 Like
11

Hi there,
I was following this thread since i had the same problems as i.ucurmak. Thus, i have few more questions if you dont mind,

  1. What is the pinmux BCT file and where can we find it ?

  2. I could not find “TEGRA_MAIN_GPIO_PORT_INFO(port, cid, cind, npins)” in gpio-tegra186.c, tegra186-gpio.h or tegra194-gpio.h. Can you point me to correct files ?
    ( i have downloaded source code and the drivers through this link L4T 32.5.1 drivers and source files )

12

hello berkay.kocak,

you should see the documentation, MB1 Configuration Changes. you must customize the spreadsheet for the configuration of your board. please download pinmux spreadsheets to have customization.

please check below for the definition of TEGRA_MAIN_GPIO_PORT_INFO,
for example,
$L4T_Sources/r32.5.1/Linux_for_Tegra/source/public/kernel/nvidia/drivers/gpio/gpio-tegra186.c

note,
tegra186-gpio.h is only used by Jetson TX2 series. Jetson Xavier series is using the header file with t194 series.
for example,
$L4T_Sources/r32.5.1/Linux_for_Tegra/source/public/kernel/nvidia/include/dt-bindings/gpio/tegra194-gpio.h

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