Hi,
I’m trying to write a kernel module for the Jetson Nano 2GB. However, I cannot find documentation on how the Jetson Nano 2GB header pins map to the Tegra X1 SoC address map. Are there any data sheets for this? I’ve read through the Tegra X1 Soc TRM and the Jetson Nano 2GB provided data sheets, and have found no luck.
Thanks,
Jonathan