Jetson Nano 2GB Carrier Board and Direct Memory Access

Hi,

I’m trying to write a kernel module for the Jetson Nano 2GB. However, I cannot find documentation on how the Jetson Nano 2GB header pins map to the Tegra X1 SoC address map. Are there any data sheets for this? I’ve read through the Tegra X1 Soc TRM and the Jetson Nano 2GB provided data sheets, and have found no luck.

Thanks,
Jonathan

sorry, can you elaborate a bit on the problem statement?
could not understand pins with address. You want to know the register address for the pins on the CVB?

Sorry, let me clarify. Looking at the Jetson Nano Pin Mux Excel Sheet, say for Pin 12 on the header pins, it can be configured as either GPIO3_PJ.07 or I2S4B_SCLK. My question is, how does the naming convention GPIO3_PJ.07, tie to the Tegra X1 SoC TRM gpio controller. I understand we have GPIO1-GPIO8 with Ports A-Z. Would this mean, this is gpio controller GPIO3 on Port J, pin 7? I’m referring to the Tegra X1 SoC Technical Reference Manual found Tegra Linux Driver. I’m having a hard time mapping this naming convention to find the register address.

Correct!
GPIO3_PJ.07 means GPIO3 on Port J, pin 7
Each GPIO controller has 4 ports.
Each port has 8 pins.
Since GPIO3 controller address from TRM is 0x6000d200, GPIO3 Port J address will be 0x6000d204. Bit 7 of this register denotes Pin 7 status.
Similary Port K address will be 0x6000d208.
You can find more info in GPIO registers section of TRM.

Thanks,
Shubhi

Hey shgarg, this is where I get confused. In this thread, Jetson Nano GPIO control through direct memory access with C++ - implementation and examples? - #11 by trueshadow97, you gave the base address for GPIO3_PC.00, the address 0x6000d000. Shouldn’t it also be 0x600d200 also in this case for GPIO3?

GPIO controller base address is 0x6000d000. Since 8 gpio controllers:
So for Port A: address is 0x6000d000
B: 0x6000d004
C: 0x6000d008
D: 0x6000d00c
E: 0x6000d100
F: 0x6000d104
etc
Therefore, J is 0x6000d204

One correction: GPIO3_XXX does not mean 3rd gpio controller. Refer port number, GPIOy_Pxx
to get correct mapping.
A,B,C,D falls on GPIO1
E,F,G,H - GPIO2
I,J,K,L- GPIO3 and so on.

Wonderful! Thank you so much Shubi!!

Shubhi*