pvalue
September 14, 2023, 6:29am
1
Hi,
I am using A205 carrier board with Jetson Nano production module, 36.6.1 L4T version with Jetpack 4.6. I want to use the 40-pin header of the A205 carrier board and want to enable 2 GPIOs. I have followed the flashing procedure according to this A205 Carrier Board | Seeed Studio Wiki , but I was not able to see the 40-pin header by using Jetson-IO, it is showing only CSI connector.
I even tried to change make changes in pinmux and device tree by following this https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-3261/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/adaptation_and_bringup_nano.html#wwpID0E0RQ0HA
But still not able to see the 40-pin header by using Jetson-IO.
Are there any device tree changes that i need to do? or Do I need follow any specific procedure?
Please help.
Thank you
Hi,
jetson-io does not support jetson nano emmc module.
The purpose of jetson-io is to configure pinmux… so if you already updated the device tree and pinmux, then you don’t need to use jetson-io again… this is just duplicated work.
pvalue
September 14, 2023, 10:17am
3
Thanks for the Reply!
Do I also need to follow “Porting U-Boot” in this https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-3261/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/adaptation_and_bringup_nano.html#wwpID0E0PO0HA "
After I have updated pinmux, device tree image and reflashed? I just want to work with 2 GPIOs of the carrier board.
Hi,
What do you want to do here exactly?
A pinmux is just a thing to configure the role of the pin. For example, a pin could be either gpio or sfio. GPIO could be configured as output high/low or input by default.
The problem here is, after you configure it as GPIO, you need some extra application or driver to use it.
I feel what you are doing here is “the pin is already configured as gpio, but no one is using it”.
pvalue
September 14, 2023, 11:55am
5
I want to use HX711 amplifier and load cell to get weights, for this I want GPIOs of A205 Board and connect it to DOUT and PD_SCK of HX711.
Hi,
It does not matter to me what you want to use over here. For example, HX711 or even just want to use GPIO to turn on a LED.
The question here is just
What gpio do you want to use? Which pin?
What is this gpio going to do? A input? A output? static output high? or output low? Or dynamic controlled?
pvalue
September 14, 2023, 12:25pm
7
I want to use one GPIO for input (DOUT) and the other for output (PD_SCK).
Then, i need to do the following:
Wait for the DOUT pin to go low.
Pulse the PD_SCK pin 24 times and read the DOUT pin each time, collecting the 24-bit data.
I want to use pins 27 and 11 as the GPIO pins (11 - in, 27 - OUT)
Hi,
What you need to learn the linux gpio sysfs. It does not matter to jetson. It is a common interface on linux.
https://www.kernel.org/doc/Documentation/gpio/sysfs.txt
pvalue
September 14, 2023, 1:35pm
9
I have already used this “echo 27 > /sys/class/gpio/export”, set its direction as out, then check its value by using “cat /sys/class/gpio/gpio27/value”
But the value of GPIO is not changing when I am applying Gnd or Vcc.
Will the value of GPIO I am using here be the same as that of the 40 pin header board or will it change according to kernel or device configuration?
Hi,
No, they are not same. GPIO pin number is not 40 pin header number. So using 27 to it is wrong.
Please tell what is the GPIO name you saw in the pinmux spreadsheet.
I mean there is something like GPIO3_PXX.X in the row. I need the value there. Not DOUT or PD_SCK.
whoelse
September 15, 2023, 5:38am
11
Hey WayneWWW,
Thanks for the help, I work with pvalue.
The GPIO names are: GPIO3_PG.02 and GPIO3_PJ.07
I understand these map to pins 11 and 12 on the 40 pin expansion header.
please also dump
sudo -s
cat /sys/kernel/debug/gpio
whoelse
September 15, 2023, 7:16am
13
gpiochip0: GPIOs 0-255, parent: platform/6000d000.gpio, tegra-gpio:
gpio-0 ( )
gpio-1 ( )
gpio-2 ( |pcie_wake ) in hi
gpio-3 ( )
gpio-4 ( )
gpio-5 ( )
gpio-6 ( |system-suspend-gpio ) out hi
gpio-7 ( )
gpio-8 ( )
gpio-9 ( )
gpio-10 ( )
gpio-11 ( )
gpio-12 (SPI1_MOSI )
gpio-13 (SPI1_MISO )
gpio-14 (SPI1_SCK )
gpio-15 (SPI1_CS0 )
gpio-16 (SPI0_MOSI )
gpio-17 (SPI0_MISO )
gpio-18 (SPI0_SCK )
gpio-19 (SPI0_CS0 )
gpio-20 (SPI0_CS1 )
gpio-21 ( )
gpio-22 ( )
gpio-23 ( )
gpio-24 ( )
gpio-25 ( )
gpio-26 ( )
gpio-27 ( )
gpio-28 ( )
gpio-29 ( )
gpio-30 ( )
gpio-31 ( )
gpio-32 ( )
gpio-33 ( )
gpio-34 ( )
gpio-35 ( )
gpio-36 ( )
gpio-37 ( )
gpio-38 (GPIO13 )
gpio-39 ( )
gpio-40 ( )
gpio-41 ( )
gpio-42 ( )
gpio-43 ( )
gpio-44 ( )
gpio-45 ( )
gpio-46 ( )
gpio-47 ( )
gpio-48 ( )
gpio-49 ( )
gpio-50 (UART1_RTS )
gpio-51 (UART1_CTS )
gpio-52 ( )
gpio-53 ( )
gpio-54 ( )
gpio-55 ( )
gpio-56 ( )
gpio-57 ( )
gpio-58 ( )
gpio-59 ( )
gpio-60 ( )
gpio-61 ( )
gpio-62 ( )
gpio-63 ( )
gpio-64 ( |i2c-mux-gpio ) out hi
gpio-65 ( |? ) out hi
gpio-66 ( )
gpio-67 ( )
gpio-68 ( )
gpio-69 ( )
gpio-70 ( )
gpio-71 ( )
gpio-72 ( )
gpio-73 ( )
gpio-74 ( )
gpio-75 ( )
gpio-76 (I2S0_FS )
gpio-77 (I2S0_DIN )
gpio-78 (I2S0_DOUT )
gpio-79 (I2S0_SCLK )
gpio-80 ( )
gpio-81 ( )
gpio-82 ( )
gpio-83 ( )
gpio-84 ( )
gpio-85 ( )
gpio-86 ( )
gpio-87 ( )
gpio-88 ( )
gpio-89 ( )
gpio-90 ( )
gpio-91 ( )
gpio-92 ( )
gpio-93 ( )
gpio-94 ( )
gpio-95 ( )
gpio-96 ( )
gpio-97 ( )
gpio-98 ( )
gpio-99 ( )
gpio-100 ( )
gpio-101 ( )
gpio-102 ( )
gpio-103 ( )
gpio-104 ( )
gpio-105 ( )
gpio-106 ( )
gpio-107 ( )
gpio-108 ( )
gpio-109 ( )
gpio-110 ( )
gpio-111 ( )
gpio-112 ( )
gpio-113 ( )
gpio-114 ( )
gpio-115 ( )
gpio-116 ( )
gpio-117 ( )
gpio-118 ( )
gpio-119 ( )
gpio-120 ( )
gpio-121 ( )
gpio-122 ( )
gpio-123 ( )
gpio-124 ( )
gpio-125 ( )
gpio-126 ( )
gpio-127 ( )
gpio-128 ( )
gpio-129 ( )
gpio-130 ( )
gpio-131 ( )
gpio-132 ( )
gpio-133 ( )
gpio-134 ( )
gpio-135 ( )
gpio-136 ( )
gpio-137 ( )
gpio-138 ( )
gpio-139 ( )
gpio-140 ( )
gpio-141 ( )
gpio-142 ( )
gpio-143 ( )
gpio-144 ( )
gpio-145 ( )
gpio-146 ( )
gpio-147 ( )
gpio-148 ( )
gpio-149 (GPIO01 )
gpio-150 ( )
gpio-151 ( )
gpio-152 ( )
gpio-153 ( )
gpio-154 ( )
gpio-155 ( )
gpio-156 ( )
gpio-157 ( )
gpio-158 ( )
gpio-159 ( )
gpio-160 ( )
gpio-161 ( )
gpio-162 ( )
gpio-163 ( )
gpio-164 ( )
gpio-165 ( )
gpio-166 ( )
gpio-167 ( )
gpio-168 (GPIO07 )
gpio-169 ( )
gpio-170 ( )
gpio-171 ( )
gpio-172 ( )
gpio-173 ( )
gpio-174 ( )
gpio-175 ( )
gpio-176 ( )
gpio-177 ( )
gpio-178 ( )
gpio-179 ( )
gpio-180 ( )
gpio-181 ( )
gpio-182 ( )
gpio-183 ( )
gpio-184 ( )
gpio-185 ( )
gpio-186 ( )
gpio-187 ( )
gpio-188 ( )
gpio-189 ( |Power ) in hi IRQ
gpio-190 ( |Forcerecovery ) in hi IRQ
gpio-191 ( )
gpio-192 ( )
gpio-193 ( )
gpio-194 (GPIO12 )
gpio-195 ( )
gpio-196 ( )
gpio-197 ( )
gpio-198 ( )
gpio-199 ( )
gpio-200 (GPIO11 )
gpio-201 ( )
gpio-202 ( |pwm-fan-tach ) in hi IRQ
gpio-203 ( |vdd-3v3-sd ) out lo
gpio-204 ( )
gpio-205 ( )
gpio-206 ( )
gpio-207 ( )
gpio-208 ( )
gpio-209 ( )
gpio-210 ( )
gpio-211 ( )
gpio-212 ( )
gpio-213 ( )
gpio-214 ( )
gpio-215 ( )
gpio-216 (GPIO09 )
gpio-217 ( )
gpio-218 ( )
gpio-219 ( )
gpio-220 ( )
gpio-221 ( )
gpio-222 ( )
gpio-223 ( )
gpio-224 ( )
gpio-225 ( |hdmi2.0_hpd ) in lo IRQ
gpio-226 ( )
gpio-227 ( )
gpio-228 ( |extcon:extcon@1 ) in lo IRQ
gpio-229 ( )
gpio-230 ( )
gpio-231 ( |? ) out hi
gpio-232 (SPI1_CS1 )
gpio-233 ( )
gpio-234 ( )
gpio-235 ( )
gpio-236 ( )
gpio-237 ( )
gpio-238 ( )
gpio-239 ( )
gpiochip1: GPIOs 504-511, parent: platform/max77620-gpio, max77620-gpio, can sleep:
gpio-505 ( |spmic-default-output) out hi
gpio-507 ( |vdd-3v3-sys ) out hi
gpio-510 ( |enable ) out hi
gpio-511 ( |avdd-io-edp-1v05 ) out lo
whoelse
September 15, 2023, 12:17pm
14
gpio_output.txt (8.5 KB)
Dump attached.
Please refer to this txt file.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for binding nvidia,tegra*-gpio.
*
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
* provide names for this.
*
* The second cell contains standard flag values specified in gpio.h.
*/
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
#include <dt-bindings/gpio/gpio.h>
#define TEGRA_GPIO_PORT_A 0
#define TEGRA_GPIO_PORT_B 1
#define TEGRA_GPIO_PORT_C 2
#define TEGRA_GPIO_PORT_D 3
#define TEGRA_GPIO_PORT_E 4
This file has been truncated. show original
The calculation here is you have to know the offset from above file you shared first.
gpiochip0: GPIOs 0 -255, parent: platform/6000d000.gpio, tegra-gpio:
This line tells that the GPIO offset is from 0.
If you want to use PG.02 pin, then it means it is the second pin of the port “G”.
From the txt file, port G is with number 6.
define TEGRA_GPIO_PORT_G 6
And according to the formula in the txt file.
((TEGRA_GPIO_PORT_#port * 8) + offset)
To calculate PG.02, it should be 6*8 +2 + 0 (2 means the second pin in port G. 0 means the offset from the txt file you attached).
So “50” is the number you should export.
1 Like
system
Closed
September 29, 2023, 2:47pm
16
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