r32.3.1 gpio question

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

This is your documentation. I believe it is bad, it would mean that gpios are every eight mapping and only there are only 24 gpios.

GPIO Changes
If you designed your own carrier board, to translate from SOM-connector pins to actual GPIO numbers you must understand GPIO mapping formula below. The translated GPIO numbers can be controlled by the driver.
For example, to check the GPIO number of GPIO15/AP2MDM_READY. perform the following steps.
To check the GPIO number
1.Search for GPIO15_AP2MDM_READY in Jetson_TX2_Generic_Customer_Pinmux_Release.xlsx.
2.Confirm that the Customer Usage field is applied to GPIO3_PBB.00.
3.Confirm in tegra186-gpio.h that GPIO3_PBB.00 belongs to the main Jetson GPIO group, and that the port number is 21:
#define TEGRA_MAIN_GPIO_PORT_BB 21
4.Because the SoC device registers GPIOs dynamically, search kernel messages to check GPIO allocation ranges for each GPIO group. The command and resulting output are similar to the following:
$ dmesg | grep gpiochip_add_data
[ 1.247404] gpiochip_add_data: registered GPIOs 320 to 511 on device: tegra-gpio
[ 1.262595] gpiochip_add_data: registered GPIOs 256 to 319 on device: tegra-gpio-aon
As shown in the outpout above, there are two Jetson GPIO ports with different offsets:
•tegra-gpio, offset = 320
•tegra-gpio-aon, offset= 256
5.Because PBB00 belongs to the tegra-gpio group, the port number from step 3 is 21, and the offset is 320. Use the following formula to calculate the GPIO number:
TEGRA_MAIN_GPIO(port, offset) = ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
Hence, the GPIO number of GPIO15/AP2MDM_READY is (21*8)+320 = 488.

This is the output from sudo cat /sys/kernel/debug/gpio

gpiochip4: GPIOs 216-223, parent: platform/max77620-gpio, max77620-gpio, can sleep:
gpio-216 ( |external-connection:) in hi
gpio-221 ( |spmic_gpio_input ) in lo
gpio-222 ( |spmic_gpio_input ) in hi

gpiochip3: GPIOs 224-239, parent: i2c/0-0077, tca9539, can sleep:
gpio-227 ( |en-vdd-sys ) out lo
gpio-228 ( |lcd-bias-rails ) out hi
gpio-233 ( |en-vdd-cam ) out lo
gpio-234 ( |en-vdd-cam-1v2 ) out lo

gpiochip2: GPIOs 240-255, parent: i2c/0-0074, tca9539, can sleep:
gpio-240 ( |vdd-usb2-5v ) out lo
gpio-241 ( |en-vdd-ts-1v8 ) out hi
gpio-242 ( |en-vdd-ts-hv-3v3 ) out hi
gpio-243 ( |en-vdd-disp-3v3 ) out lo
gpio-244 ( |vdd-fan ) out lo
gpio-247 ( |en-mdm-pwr-3v7 ) out lo
gpio-249 ( |en-vdd-disp-1v8 ) out lo
gpio-250 ( |dis-vdd-1v2 ) out hi
gpio-252 ( |vdd-hdmi ) out hi
gpio-253 ( |en-vdd-cam-hv-2v8 ) out lo

gpiochip1: GPIOs 256-319, parent: platform/c2f0000.gpio, tegra-gpio-aon:
gpio-272 ( |temp-alert ) in hi
gpio-312 ( |Power ) in hi
gpio-313 ( |Volume Up ) in hi
gpio-314 ( |Volume Down ) in hi
gpio-315 ( |wifi-wake-ap ) in lo
gpio-316 ( |bt_host_wake ) in lo

gpiochip0: GPIOs 320-511, parent: platform/2200000.gpio, tegra-gpio:
gpio-376 ( |sysfs ) out lo
gpio-381 ( |reset_gpio ) out lo
gpio-412 ( |vdd-usb0-5v ) out lo
gpio-413 ( |vdd-usb1-5v ) out lo
gpio-420 ( |eqos_phy_reset ) out hi
gpio-424 ( |wlan_pwr ) out hi
gpio-426 ( |camera-control-outpu) out lo
gpio-441 ( |hdmi2.0_hpd ) in lo
gpio-444 ( |wp ) in lo
gpio-445 ( |cd ) in hi
gpio-446 ( |en-vdd-sd ) out lo
gpio-456 ( |camera-control-outpu) out lo
gpio-457 ( |camera-control-outpu) out lo
gpio-461 ( |camera-control-outpu) out lo
gpio-479 ( |external-connection:) in lo
gpio-484 ( |bt_ext_wake ) out hi

it clearly breaks you scheme because gpio-412 and gpio-413 are not “seperated by 8”

So what is the real mapping solution?

WayneWWW do you have some more documentation to fix?

I want to get to gpio7 which is a gpio line to my mipi dsi device.

Terry

2

Hi,

>               vdd_usb0_5v: regulator@4 {
                        compatible = "regulator-fixed-sync";
                        reg = <4>;
                        regulator-name = "vdd-usb0-5v";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(L, 4) 0>;
                        gpio-open-drain;
                        enable-active-high;
                };

                vdd_usb1_5v: regulator@5 {
                        compatible = "regulator-fixed-sync";
                        reg = <5>;
                        regulator-name = "vdd-usb1-5v";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(L, 5) 0>;
                        gpio-open-drain;
                        enable-active-high;
                };

TEGRA_MAIN_GPIO(L, 4) is 4 + (11*8) + 320 = gpio-412. The logic looks correct. Please share why you think gpio-412,gpio-413 are not separated by 8.

3

where is tegra_main_gpio TEGRA_MAIN_GPIO documented.

Where did (L,4) and (L,5) come from? Where is that documented?

Why in your main documentation do you never mentions the .00 in GPIO3_PBB.00.

Why don’t you just put the value of gpio to add to the 320 or 256 in the spreadsheet.

The spreadsheet need to specify the MAIN or AON information also.

4

Hi,
The two pins are A17, A18 in product design guide:
https://developer.nvidia.com/embedded/dlc/jetson-tx2-series-oem-product-design-guide

If you don’t have customization in USB lane mapping, the two pins are used for USB functions. If you would like to customize USB lane mapping, please check adaptation guide: