GPIO numbering - mapping to sysfs GPIO for JETSON XAVIER

Hi All,

Referring to the following link: https://www.jetsonhacks.com/nvidia-jetson-agx-xavier-gpio-header-pinout/

I know that PIN32 of 40 pins header - GPIO9_CAN1_GPIO0_DMIC_CLK mapped to GPIO257 of sysfs GPIO.

However, when I trace the source code, it has not been matched. Here are the below steps.

  1. As per Jetson_AGX_Devkit_Pinmux_Configuration_Template.xlsm, this pin mapped to GPIO3_PBB.01

  2. …/Linux_for_Tegra/sources/kernel/kernel-4.9/include/dt-bindings/gpio/tegra-gpio.h defined

#define TEGRA_GPIO_PORT_BB 27
...
#define TEGRA_GPIO(port, offset) \
	((TEGRA_GPIO_PORT_##port * 8) + offset)

Finally,

PIN32 mapping --> (27*8+1) = 217

Please anyone let me know if something wrongs here. Thanks a lot!

Hi,

The correct gpio header should be “kernel/nvidia/include/dt-bindings/gpio/tegra194-gpio.h.”.

You should also check the gpio range by this node

root@tegra-ubuntu:/sys/kernel/debug/pinctrl/2430000.pinmux# cat gpio-ranges 
GPIO ranges handled:
0: Tegra GPIOs GPIOS [0 - 252] PINS [0 - 252]
0: tegra-gpio GPIOS [320 - 463] PINS [0 - 143]
144: tegra-gpio GPIOS [464 - 471] PINS [152 - 159]
152: tegra-gpio GPIOS [472 - 487] PINS [184 - 199]
168: tegra-gpio GPIOS [488 - 511] PINS [216 - 239]
0: tegra-gpio-aon GPIOS [256 - 263] PINS [144 - 151]
8: tegra-gpio-aon GPIOS [264 - 287] PINS [160 - 183]
32: tegra-gpio-aon GPIOS [288 - 303] PINS [200 - 215]
48: tegra-gpio-aon GPIOS [304 - 319] PINS [240 - 255]

Please note that above node is from TX2 because I am out of AGX now. But the node name should be similar.

Hi Wayne,

Thanks a lot for your comment!

However, the correct header may not be the one you gave, because I used dtsi file generated by jetson_agx_devkit.xlsm. The generated file included tegra-gpio.h only.

/*This dtsi file was generated by jetson_agx_devkit.xlsm Revision: 1.03 */
/*
 * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <dt-bindings/gpio/tegra-gpio.h>

/ {
	gpio@2200000 {
		gpio-init-names = "default";
		gpio-init-0 = <&gpio_default>;

		gpio_default: default {
			gpio-input = <
				...
                                ...
				TEGRA_GPIO(BB, 0)
				TEGRA_GPIO(BB, 1) // <-- I am looking for this one
				TEGRA_GPIO(BB, 2)
                                ...

Following that included file <dt-bindings/gpio/tegra-gpio.h>, I found

...
#define TEGRA_GPIO_BANK_ID_BB 27
...

#define TEGRA_GPIO(bank, offset) \
	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)

From this, I know that

PIN32 mapping --> GPIO3_PBB.01 --> (27*8+1) = 217 --> PIN217

I verified again in /sys/kernel/debug/pinctrl/2430000.pinmux# cat pins, the result told that

pin 217 (CAN1_EN_PBB1) 2430000.pinmux

Then run

cat gpio-ranges

GPIO ranges handled:

0:tegra-gpio-aon GPIOS [248-287] PIN [208 - 247]

With respect to GPIOS <–> PIN mapping above. PIN 217 mapped to GPIO257

And “kernel/nvidia/include/dt-bindings/gpio/tegra194-gpio.h.” info not different from the one I traced.

Hi,

I am little bit confused by the tool “jetson_agx_devkit.xlsm”. Where did it come from? Which release are you using? I just checked all dtsi files in rel-32 kernel and notice that only platforms prior to TX2 are using this file.

As for the gpio range, per checked tegra194-gpio.h

#define TEGRA194_AON_GPIO_PORT_BB 1
-> 1*8+1 and this one is AON_GPIO, w.r.t below gpio ranges

GPIO ranges handled:
0: tegra-gpio GPIOS [288 - 495] PINS [0 - 207]
208: tegra-gpio GPIOS [496 - 511] PINS [248 - 263]
0: tegra-gpio-aon GPIOS [248 - 287] PINS [208 - 247]

The gpio number should be 248 + 1*8+1 = gpio 257 and the pin is mapping to 208+9 = 217.

Please also note that the macro “TEGRA_GPIO” is also used by < TX2 platforms too.

From my understanding, the excel macro file is only applicable for JETSON_AGX, you can refer to the link from Nvidia:

Link to download https://developer.nvidia.com/embedded/dlc/jetson-xavier-pinmux

Hopefully this tool is still valid for Jetson Xavier board.

Hi,

Yes, this file is valid. But the file name is “Jetson_AGX_Devkit_Pinmux_Configuration_Template.xlsm” and it is for mb1 pinmux but not kernel.

When calculating the gpio number, please refer to tegra194-gpio.h for xavier and tegra186-gpio.h for TX2.

Thanks a lot, Wayne!