you may check pinmux spreadsheets, that GPIO17 (i.e. GPIO3_PQ.01) were configure as pull-down by default.
could you please customize that for updating board configuration.
thanks
I need to control GPIO17 to output high or low level to feed watchdog in cboot ,so I must use tegrabl_gpio_write and tegrabl_gpio_config.
If GPIO17 (i.e. GPIO3_PQ.01) were configure as pull-down by default, can i still control it to output different levels?
I think you’re miscalculate GPIO number for controlling.
according to gpio header, GPIO3_PQ.01 should belong to main GPIO controller groups. $L4T_Sources/r32.4.2/Linux_for_Tegra/source/public/kernel/nvidia/include/dt-bindings/gpio/tegra194-gpio.h
I run “feed_wdt()” in cboot_src_t19x/bootloader/partner/common/drivers/gpio/tegrabl_gpio.c.
My cboot_src_t19x code is running on Xavier platform.
Whether or not you have verified these functions
(
.read = &tegrabl_gpio_read,
.write = &tegrabl_gpio_write,
.config = &tegrabl_gpio_config
)?
I add some debug prints.It shows that running code has enter this function gpio_config(),
error = gpio_config(gpio_drv, gpio_num, GPIO_PINMODE_OUTPUT);
if (error != TEGRABL_NO_ERROR) {
pr_error(“%s: Error config gpio pin\n”, func);
return error;
}
But gpio_config return error.
I have solved this problem.
The parameter gpio_num is the value of (port*8)+pin, not include group.
SO in this function, GPIO17(GPIO3_PQ.01) will be 129.
I am also trying to control GPIO in Cboot. I have followed the same way as mentioned above. But I am not able to control the GPIO.
I am using Jetson AGX Xavier. trying to control the GPIO3_PBB.00 (routed to 40-pin GPIO Header)
This GPIO is on TEGRA_GPIO_AON_CHIPID. And I followed the same calculation to get gpio_num:
(port*8)+pin
(TEGRA_GPIO_BANK_ID_BB * 8) + pin = (1 * 8) + 0 = 8.
But I used to control the same GPIO in my kernel modules using
(TEGRA_GPIO_BANK_ID_BB * 8) + offset = (1 * 8) + 248 = 256.
If I give gpio_num = 256. I will get invalid GPIO. and If I give 8. Not getting any Error. But GPIO is not toggling as per my code.
I have added a code snippet below I have added this snippet in tegrabl_gpio.c :
Thanks for input. I changed the pin to 168. And tested the same. Still I am not able to control the i/o.
Below is the some of the Logs I have taken :
[0002.294] I> gpio_validation: check pin in Cboot = 168
[0002.294] I> tegrabl_gpio_config: gpio_num = 168, mode = 1, id = 0xa0667508
[0002.300] I> is_gpio_valid: bank = 21, bank_Max = 28
[0002.305] I> tegrabl_gpio_write: gpio_num = 168, state = 1, id = 0xa0667508
[0002.312] I> is_gpio_valid: bank = 21, bank_Max = 28
[0003.317] I> tegrabl_gpio_write: gpio_num = 168, state = 0, id = 0xa0667508
[0003.317] I> is_gpio_valid: bank = 21, bank_Max = 28
[0003.318] I> tegrabl_gpio_write: gpio_num = 168, state = 1, id = 0xa0667508
[0003.318] I> is_gpio_valid: bank = 21, bank_Max = 28
[0004.319] I> tegrabl_gpio_write: gpio_num = 168, state = 0, id = 0xa0667508
[0004.319] I> is_gpio_valid: bank = 21, bank_Max = 28
I have added, Above mentioned snippet in “tegrabl_gpio.c” and I am calling my function from “platform.c”.
Any device tree change is required. ?
We need to use #define TEGRA194_AON_GPIO_PORT_BB 1 only. After making the pin num as 8. and configured as an input and tried to read the status of i/o it is working. But still as a output I am not able to toggle the i/o. I am using oscilloscope to probe the signals to check the i/o toggle.
[0124.506] I> is_gpio_valid: bank = 1, bank_Max = 5
[0125.007] I> grl_gpio_validation: Pin Read Value = 0 — Pin-16 connected to GND
[0125.007] I> is_gpio_valid: bank = 1, bank_Max = 5
[0125.507] I> grl_gpio_validation: Pin Read Value = 1 — Pin-16 connected to 3.3V
And I confirmed the respective GPIO is a part of A-ON not from MAIN GPIO Controller
gpiochip1: GPIOs 248-287, parent: platform/c2f0000.gpio, tegra-gpio-aon:
gpio-253 ( |pex-refclk-sel-low ) out lo gpio-256 ( |sysfs ) out hi
gpio-284 ( |power-key ) in hi
After changing the pin num to 8 and as input. I am able to get the status of the i/o. But as a output. I am not able to control. And the HW is working fine. I verified from user space application.
it’s correct that you should refer to tegra194-gpio.h for Xavier’s GPIO definition.
i.e. #define TEGRA194_AON_GPIO_PORT_BB 1
you may check kernel messages for the AON-GPIO allocation range, it’s starting from 248.
i.e. [ 0.882955] gpiochip_setup_dev: registered GPIOs 248 to 287 on device: gpiochip1 (tegra-gpio-aon)
so,
let me correct my previous comments, this pin GPIO3_PBB.00, GPIO number = 1*8+248 = 256.
Yes. Based on that kernel log messages and I derived the respective GPIO number as 256 and keeping 256 able to control the i/o in user space application and as well kernel modules.
But in case of Cboot. I need to use below formula to calculate the GPIO Pin number. Correct ?
(port*8)+pin = (1 * 8) + 0 = 8. With Pin num as 8. and GPIO as input is working. But as output not working. for using the i/o in cboot as output any other changes required. Please let us know.
since the default pin direction of GPIO3_PBB.00 is input.
you may also have MB1 configurations to update the pin direction as output.
you may review your board configuration file to have confirmation,
for example,