L4T : R35.3.1
GPIO02(Orin NX pin124,GPIO3_PP.06) can’t output high level.Normal input function.
$ echo 446 > /sys/class/gpio/export
$ echo out > /sys/class/gpio/PP.06/direction
$ echo 1 > /sys/class/gpio/PP.06/value （can not get high leve）
hello gcs,
it the GPIO number correct? please double check $ sudo cat /sys/kernel/debug/gpio | grep PP.06
The GPIO number is correct.I can get the correct values when it is working in input mode.
hello gcs,
please check pinmux spreadsheets, this pin GPIO02/ GPIO3_PP.06 is default configured as Input, and it’s Baseboard M.2 Wake Request to AP.
No program was found to use it in the device-tree project. I want to confirm its status by reading the register address，but the new L4T no longer has ’ /sys/kernel/debug/tegra_pinctrl_reg’.
please follow below for pin register address calculation
you may also check TRM, it’s PADCTL_G3_SOC_GPIO25_0 for the register description.
note, the G3 PAD Control Registers are collectively called PADCTL_A0 in the System Address Map.
hence…
PADCTL_G3_SOC_GPIO25_0’s offset= 0x30, the pin address = 0x02430000 + 0x30 = 0x02430030,
you’re able to read the pin status with… $ sudo busybox devmem 0x02430030
root@nvidia-desktop:/home/nvidia# line=cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinconf-groups | grep -n gpio25 | cut -d : -f 1; cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinconf-groups | tail -n +$line | head -n 15
140 (soc_gpio25_pp6):
pull=0
tristate=0
enable-input=0
open-drain=0
io-reset=0
rcv-sel=0
io-hv=0
loopback=0
schmitt=0
pull-down-strength=0
pull-up-strength=0
drive-type=0
func=vi0
pad-power=0
root@nvidia-desktop:/home/nvidia# busybox devmem 0x02430030
0x00000020
This PIN is not enabled(schmitt=0) by default.Enable it by writing the register,it can now work.
Later, we will try to enable it in Device-Tree or PINMUX file.
We enabled ‘nvidia,schmitt’ in file ‘./tegra234-mb1-bct-pinmux-p3767-dp-a01.dtsi’ and then re-flash the OS.
However, this PIN remains disabled.
Is this still an issue to support? Any result can be shared? Thanks
Cannot operate this pin by SYSFS. Looks like a BSP bug.
we’ve checked locally, we can configure the pin as GPIO and the direction of the pin can be set as input/output in our pinmux device tree.
for example, you can configure the pin as GPIO output as below.
pinmux dtsi:
soc_gpio25_pp6 {
nvidia,pins = "soc_gpio25_pp6";
nvidia,function = "vi0"; --------> GPIO
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>; --------> Output
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
GPIO dtsi:
+++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
@@ -51,7 +51,6 @@
TEGRA234_MAIN_GPIO(Z, 5)
TEGRA234_MAIN_GPIO(Z, 6)
TEGRA234_MAIN_GPIO(Z, 7)
- TEGRA234_MAIN_GPIO(P, 6)
TEGRA234_MAIN_GPIO(Q, 6)
TEGRA234_MAIN_GPIO(N, 1)
TEGRA234_MAIN_GPIO(G, 0)
@@ -65,6 +64,7 @@
TEGRA234_MAIN_GPIO(L, 2)
>;
gpio-output-low = <
+ TEGRA234_MAIN_GPIO(P, 6) -------> GPIO Output with initial state 0
TEGRA234_MAIN_GPIO(H, 6)
TEGRA234_MAIN_GPIO(I, 5)
TEGRA234_MAIN_GPIO(AC, 0)
furthermore,
had you re-flash the board to update the pinmux config?
Hello @JerryChang ,
I’have the same problem with the GPIO02 (P.06)
Modified pinmux:
soc_gpio25_pp6 {
nvidia,pins = "soc_gpio25_pp6";
nvidia,function = "vi0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
};
The default GPIO
gpio@2200000 {
gpio-init-names = "default";
gpio-init-0 = <&gpio_main_default>;
gpio_main_default: default {
gpio-input = <
TEGRA234_MAIN_GPIO(B, 0)
TEGRA234_MAIN_GPIO(X, 7)
TEGRA234_MAIN_GPIO(Y, 3)
TEGRA234_MAIN_GPIO(Z, 1)
TEGRA234_MAIN_GPIO(P, 2)
TEGRA234_MAIN_GPIO(P, 3)
TEGRA234_MAIN_GPIO(Q, 2)
TEGRA234_MAIN_GPIO(Q, 6)
TEGRA234_MAIN_GPIO(M, 0)
TEGRA234_MAIN_GPIO(N, 1)
TEGRA234_MAIN_GPIO(G, 0)
TEGRA234_MAIN_GPIO(G, 6)
TEGRA234_MAIN_GPIO(G, 7)
TEGRA234_MAIN_GPIO(H, 7)
TEGRA234_MAIN_GPIO(AC, 0)
TEGRA234_MAIN_GPIO(AC, 6)
TEGRA234_MAIN_GPIO(L, 2)
TEGRA234_MAIN_GPIO(A, 4)
TEGRA234_MAIN_GPIO(A, 5)
TEGRA234_MAIN_GPIO(A, 7)
>;
gpio-output-low = <
TEGRA234_MAIN_GPIO(X, 6)
TEGRA234_MAIN_GPIO(Y, 4)
TEGRA234_MAIN_GPIO(Z, 6)
TEGRA234_MAIN_GPIO(Z, 7)
TEGRA234_MAIN_GPIO(P, 1)
TEGRA234_MAIN_GPIO(I, 0)
TEGRA234_MAIN_GPIO(I, 1)
TEGRA234_MAIN_GPIO(I, 5)
TEGRA234_MAIN_GPIO(K, 4)
TEGRA234_MAIN_GPIO(K, 5)
TEGRA234_MAIN_GPIO(A, 6)
>;
gpio-output-high = <
TEGRA234_MAIN_GPIO(P, 0)
TEGRA234_MAIN_GPIO(P, 6)
TEGRA234_MAIN_GPIO(Q, 3)
TEGRA234_MAIN_GPIO(Q, 5)
TEGRA234_MAIN_GPIO(H, 6)
TEGRA234_MAIN_GPIO(I, 2)
TEGRA234_MAIN_GPIO(A, 0)
>;
};
};
I just perform a complete flash but I have an error.
ormatting APP parition done
Formatting APP partition /dev/nvme0n1p1 ...
tar --xattrs -xpf /mnt/external/system.img --checkpoint=10000 --warning=no-timestamp --numeric-owner -C /tmp/ci-sjLcz7umm8
tar: Read checkpoint 10000
tar: Read checkpoint 20000
tar: Read checkpoint 30000
tar: Read checkpoint 40000
tar: Read checkpoint 50000
tar: Read checkpoint 60000
tar: Read checkpoint 70000
tar: Read checkpoint 80000
tar: Read checkpoint 90000
tar: Read checkpoint 100000
tar: Read checkpoint 110000
tar: Read checkpoint 120000
tar: Read checkpoint 130000
tar: Read checkpoint 140000
tar: Read checkpoint 150000
tar: Read checkpoint 160000
tar: Read checkpoint 170000
tar: Read checkpoint 180000
tar: Read checkpoint 190000
tar: Read checkpoint 200000
tar: Read checkpoint 210000
tar: Read checkpoint 220000
tar: Read checkpoint 230000
tar: Read checkpoint 240000
tar: Read checkpoint 250000
tar: Read checkpoint 260000
tar: Read checkpoint 270000
tar: Read checkpoint 280000
tar: Read checkpoint 290000
tar: Read checkpoint 300000
tar: Read checkpoint 310000
tar: Read checkpoint 320000
tar: Read checkpoint 330000
tar: Read checkpoint 340000
tar: Read checkpoint 350000
tar: Read checkpoint 360000
tar: Read checkpoint 370000
tar: Read checkpoint 380000
tar: Read checkpoint 390000
tar: Read checkpoint 400000
tar: Read checkpoint 410000
tar: Read checkpoint 420000
tar: Read checkpoint 430000
tar: Read checkpoint 440000
tar: Read checkpoint 450000
tar: Read checkpoint 460000
tar: Read checkpoint 470000
tar: Read checkpoint 480000
tar: Read checkpoint 490000
tar: Read checkpoint 500000
tar: Read checkpoint 510000
tar: Read checkpoint 520000
tar: Read checkpoint 530000
tar: Read checkpoint 540000
tar: Read checkpoint 550000
tar: Read checkpoint 560000
tar: Read checkpoint 570000
writing item=16, 9:0:secondary_gpt, 61203267072, 16896, gpt_secondary_9_0.bin, 16896, fixed-<reserved>-0, 57658f8ab7c1bce1e3355347bbeccc8ef93a18de
[ 944]: l4t_flash_from_kernel: Successfully flash the external device
[ 944]: l4t_flash_from_kernel: The device size indicated in the partition layout xml is smaller than the actual size. This utility will try to fix the GPT.
[ 944]: l4t_flash_from_kernel: Error flashing qspi
Flash failure
Cleaning up...
When I change from 0 to 1, I see a very small voltage increment. It switches from 0.000V to 0.030V.
Thank you.
there shows flash failure, which mean the pin configuration did not updated correctly.
Yes, I created a dedicated post about it. Do you have any idea ?
@JerryChang
I fix this error. So my board is flashed with:
soc_gpio25_pp6 {
nvidia,pins = "soc_gpio25_pp6";
nvidia,function = "vi0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
And
gpio@2200000 {
gpio-init-names = "default";
gpio-init-0 = <&gpio_main_default>;
gpio_main_default: default {
gpio-input = <
TEGRA234_MAIN_GPIO(B, 0)
TEGRA234_MAIN_GPIO(X, 7)
TEGRA234_MAIN_GPIO(Y, 3)
TEGRA234_MAIN_GPIO(Z, 1)
TEGRA234_MAIN_GPIO(P, 2)
TEGRA234_MAIN_GPIO(P, 3)
TEGRA234_MAIN_GPIO(Q, 2)
TEGRA234_MAIN_GPIO(Q, 6)
TEGRA234_MAIN_GPIO(M, 0)
TEGRA234_MAIN_GPIO(N, 1)
TEGRA234_MAIN_GPIO(G, 0)
TEGRA234_MAIN_GPIO(G, 6)
TEGRA234_MAIN_GPIO(G, 7)
TEGRA234_MAIN_GPIO(H, 7)
TEGRA234_MAIN_GPIO(AC, 0)
TEGRA234_MAIN_GPIO(AC, 6)
TEGRA234_MAIN_GPIO(L, 2)
TEGRA234_MAIN_GPIO(A, 4)
TEGRA234_MAIN_GPIO(A, 5)
TEGRA234_MAIN_GPIO(A, 7)
>;
gpio-output-low = <
TEGRA234_MAIN_GPIO(X, 6)
TEGRA234_MAIN_GPIO(Y, 4)
TEGRA234_MAIN_GPIO(Z, 6)
TEGRA234_MAIN_GPIO(Z, 7)
TEGRA234_MAIN_GPIO(P, 1)
TEGRA234_MAIN_GPIO(I, 0)
TEGRA234_MAIN_GPIO(I, 1)
TEGRA234_MAIN_GPIO(I, 5)
TEGRA234_MAIN_GPIO(K, 4)
TEGRA234_MAIN_GPIO(K, 5)
TEGRA234_MAIN_GPIO(A, 6)
>;
gpio-output-high = <
TEGRA234_MAIN_GPIO(P, 0)
TEGRA234_MAIN_GPIO(P, 6)
TEGRA234_MAIN_GPIO(Q, 3)
TEGRA234_MAIN_GPIO(Q, 5)
TEGRA234_MAIN_GPIO(H, 6)
TEGRA234_MAIN_GPIO(I, 2)
TEGRA234_MAIN_GPIO(A, 0)
>;
};
};
I take a screenshot from the oscilloscope where we saw that there is a difference (10mV) between 0 and 1 (changed with /sys/class/gpio)
Set to 0:
Set to 1:
Do you have any idea ?
Yes, sorry. A technical support from Nvidia asks me to create a new thread. I will continue on the other one.
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