GPIO setting is not work

Hi,

I would like to set GPIO pin to output-low on boot.
I moidfy cfg and dts,which are not work.

GPIO12 218 TOUCH_CLK GPIO3_PCC.04

BSP:JetPack4.4 R32.4.3
Module: Xavier-NX with emmc

dts

gpio@c2f0000 {
	gpio12_output_low {
		gpio-hog;
		output-low;
		gpios = <TEGRA194_AON_GPIO(CC, 4) 0>;
		label = "gpio12_output_low";
		status = "okay";
	};
};

dtb convert to dts

gpio@c2f0000 {
	compatible = "nvidia,tegra194-gpio-aon";
	reg-names = "security", "gpio", "gte";
	reg = <0x0 0xc2f0000 0x0 0x1000 0x0 0xc2f1000 0x0 0x1000 0x0 0xc1e0000 0x0 0x10000>;
	interrupts = <0x0 0x38 0x4 0x0 0x39 0x4 0x0 0x3a 0x4 0x0 0x3b 0x4>;
	status = "okay";
	gpio-controller;
	#gpio-cells = <0x2>;
	interrupt-controller;
	#interrupt-cells = <0x2>;
	gpio-ranges = <0xaa 0x0 0xd0 0x28>;
	linux,phandle = <0x24>;
	phandle = <0x24>;

	pex-refclk-sel-low {
		gpio-hog;
		output-low;
		gpios = <0x5 0x0>;
		label = "pex_refclk_sel_low";
		status = "disabled";
		linux,phandle = <0xb8>;
		phandle = <0xb8>;
	};

	pex-refclk-sel-high {
		gpio-hog;
		output-high;
		gpios = <0x5 0x0>;
		label = "pex_refclk_sel_high";
		status = "disabled";
		linux,phandle = <0xb9>;
		phandle = <0xb9>;
	};

	w-disable1 {
		gpio-hog;
		output-high;
		gpios = <0x12 0x1>;
		label = "w-disable1";
		status = "okay";
	};

	w-disable2 {
		gpio-hog;
		output-high;
		gpios = <0x10 0x1>;
		label = "w-disable2";
		status = "okay";
	};

	gpio12_output_low {
		gpio-hog;
		output-low;
		gpios = <0x14 0x0>;
		label = "gpio12_output_low";
		status = "okay";
	};
};

I don’t see the gpio268

I set gpio12 by pinmux,but it not work.

I modify the tegra19x-mb1-pinmux-p3668-a01.cfg below.

-pinmux.0x0c2f1280 = 0x00000001; # CONFIG CC4
-pinmux.0x0c302000 = 0x00000000; # GPIO touch_clk_pcc4

-pinmux.0x0c302000 = 0x00000056; # touch_clk_pcc4: rsvd2, pull-down, tristate-enable, input-enable, lpdr-disable
+pinmux.0x0c302000 = 0x00000406; # touch_clk_pcc4: rsvd2, pull-down, tristate-disable, input-disable, lpdr-disable

Karis

hello Karis,

you should access pinmux spreadsheets through download center to have customization,
you should customize the pinmux spreadsheet and generate the dtsi files, it should change the default pin configuration.
for example,

		gpio_default: default {
                    ...
			gpio-output-low = <
				TEGRA_GPIO(CC, 2)

you may also convert it as board configuration file (*.cfg) to flash the board. please refer to Pinmux Changes session for more details,
there’s also Configuring the 40-Pin Expansion Header to enable Jetson‑IO for pin configuration.
thanks

Hi JerryChang,

Q1: I got the dtsi files,how should I do?

Q2: In dts
The gpio11 is work fine,but gpio12 isn’t,which is in gpio@c2f0000.

	gpio11_output_low {
		gpio-hog;
		output-low;
		gpios = <TEGRA194_MAIN_GPIO(Q, 6) 0>;
		label = "gpio11_output_low";
		status = "okay";
	};

Q3 : I used pinmux-dts2cfg.py to get new configuration file (*.cfg) ,and I modified the tegra19x-mb1-pinmux-p3668-a01.cfg.

It’s not work, gpio11 and gpio12 are still input-high on boot.

Q4: Dose Configuring the 40-Pin Expansion Header can enable pin gpio11 and gpio12?

Thank you!

Karis

hello Karis,

  1. you should copy those dtsi files to your host machine, calling python script pinmux-dts2cfg.py to generate board configuration files, do not modify the cfg file, please using that to flash the board directly.

  2. GPIO12 (GPIO3_PCC.04) is the pin on baseboard 40-pin header, you may enable Jetson‑IO for pin configuration.
    thanks

Hi JerryChang,

I used configuration file from pinmux-dts2cfg.py,and enabled gpio12.
I reflashed it,but the gpio12 was still input-high,when I power on the nx.

40pin

cfg.tar.gz (3.9 KB)

Thank you!

Karis

hello Karis,

please also dump the register values for reference,

pinmux.0x02434090 = 0x00000414; # soc_gpio12_ph0: rsvd0, pull-down, tristate-enable, input-disable, lpdr-disable

for example,
$ busybox devmem 0x02434090

Hi JerryChang,

register

The gpio12 is input-high on boot(led lightup),after that gpio12 is input-low.

Thanks!

Karis

Hi Karis,

In pinmux, tegra19x-mb1-pinmux-p3668-a01.cfg:
Please try this:
from input section:
-pinmux.0x0c2f1280 = 0x00000001; # CONFIG CC4
-pinmux.0x0c302000 = 0x00000000; # GPIO touch_clk_pcc4
add in output-low section:
+pinmux.0x0c2f1280 = 0x00000003; # CONFIG CC4
+pinmux.0x0c2f128c = 0x00000000; # CONTROL CC4
+pinmux.0x0c2f1290 = 0x00000000; # OUTPUT CC4
+pinmux.0x0c302000 = 0x00000000; # GPIO touch_clk_pcc4

Do not change below setting, keep it same :
pinmux.0x0c302000 = 0x00000056; # touch_clk_pcc4: rsvd2, pull-down, tristate-enable, input-enable, lpdr-disable

Let me know the results.

Thanks,
Shubhi

Hi Shubhi,

It’s work.

Q1: Should I need to enable Jetson‑IO for pin configuration and modify dts? or Just modify cfg file?

I2S0_SCLK and GPIO11 have the same problem.

Q2: Should I use pinmux-dts2cfg.py? or Modify cfg by your way?

Signal Name Pin #
I2S0_SCLK 199
GPIO11 216

Thank you!

Karis

Hi,
If you have pinmux xls, then modify Pin Direction column of Pin TOUCH_CLK to Output and
Req Initial State to Drive 0. Then create dts from xls by clicking “Generate DT file” and create cfg from pinmux-dts2cfg.py . Likewise, same should be done for other pins.
Let me know if you are stuck somewhere.

Thanks,
Shubhi

Hi Shubhi,

Why is the Req Initial State to Drive 0?

Thank you!

Karis

Hi Karis,
When pin dir is output means it is driving. And drive 0 means drive to low value. drive 1 means drive to high value.