How to modify pinmux attribute of Xavier NX?

[frank2_hsieh1]

I would like to configure pz3 pz4 pz5 to gpio (output, pull high).
I saw the /sys/class/gpio/gpio491, gpio492, gpio493 awlays keeps input, pull low when I tried the two ways.

1. generate DTS by Jetson_Xavier_NX_Pinmux_Configuration_Template_v1.06.xlsm and covert to cfg file. Put the cfg to bootloader/t186ref/BCT and flash the image to board.

2. add the following pinmux attribute to dts file and flash the dtb to board. The result still keeps input low.
   spi1_sck_pz3 {
   nvidia,pins = “spi1_sck_pz3”;
   nvidia,function = “rsvd1”;
   nvidia,pull = <TEGRA_PIN_PULL_UP>;
   nvidia,tristate = <TEGRA_PIN_DISABLE>;
   nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   nvidia,lpdr = <TEGRA_PIN_DISABLE>;
   };

                    spi1_miso_pz4 {
                            nvidia,pins = "spi1_miso_pz4";
                            nvidia,function = "rsvd1";
                            nvidia,pull = <TEGRA_PIN_PULL_UP>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                    };
   
                    spi1_mosi_pz5 {
                            nvidia,pins = "spi1_mosi_pz5";
                            nvidia,function = "rsvd1";
                            nvidia,pull = <TEGRA_PIN_PULL_UP>;
                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                    };
   

[JerryChang]

hello frank2_hsieh1,

could you please check debug node to confirm the pin configuration.
i.e. # cat /sys/kernel/debug/gpio

[frank2_hsieh1]

Hi Jerry,

I tried it before your comment.
Now I find the others feedback about the issue.

GPIO setting is not work

Hi, I would like to set GPIO pin to output-low on boot. I moidfy cfg and dts,which are not work. GPIO12 218 TOUCH_CLK GPIO3_PCC.04 BSP:JetPack4.4 R32.4.3 Module: Xavier-NX with emmc dts gpio@c2f0000 { gpio12_output_low { gpio-hog; output-low; gpios = <TEGRA194_AON_GPIO(CC, 4) 0>; label = "gpio12_output_low"; status = "okay"; }; }; dtb convert to dts gpio@c2f0000 { compatible = "nvidia,tegra194-gpio-aon"; reg-names = "security", "gpio", "gte"; reg = <0x0 0xc2f0000 0x0 0x10…

I modify cfg as follows, export gpio491 and read gpio status of debugfs.
-pinmux, 0x02212460 = 0x00000000; config Z3
+pinmux, 0x02212460 = 0x00000003; config Z3

$sudo cat /sys/kernel/debug/gpio |grep 491
gpio-491(SPI0_SCK | sysfs ) out lo

I generated .cfg file by the tool of Jetpack 4.5.1 and I compared to the default .cfg file.
I cannot find config Z3 on .cfg file that generated by me.
I think the issue is related to the tool.
I would like to set default pull high, please teach me how to pull high it on .cfg file.
If it does work, can you provide the method to modified pinmux by dts?

[JerryChang]

hello frank2_hsieh1,

could you please share your commands to use python script to convert those file as cfg format.
for example, you should assign the dtsi file, tegra19x-jetson_xavier_nx_module-pinmux.dtsi which include your pz3, pz4, pz5 settings.
please also refer to $OUT/Linux_for_Tegra/kernel/pinmux/t19x/README.txt for pinmux-dts2cfg.py’s sample commands.

[frank2_hsieh]

There are my steps, would you try to modify pz3, pz4, pz5 to gpio default pull high? Could you give me your steps, thank you.
$cd kernel/pinmux/t19x/
$sudo python pinmux-dts2cfg.py --pinmux addr_info.txt gpio_addr_info.txt por_val.txt --mandatory_pinmux_file mandatory_pinmux.txt temp/tegra19x-jetson_xavier_nx_module-pinmux.dtsi temp/tegra19x-jetson_xavier_nx_module-gpio-default.dtsi 1.0 > product_nv.cfg
$mv product_nv.cfg …/…/…/bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p3668-a01.cfg
And flash image via
＄ssudo ./flash.sh -r jetson-xavier-nx-devkit-emmc mmcblk0p1

[JerryChang]

hello frank2_hsieh

could you please share the results by following,
# cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinmux-pins | grep PZ

[frank2_hsieh]

cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinmux-pins |grep PZ

pin 200 (UART5_CTS_PZ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 201 (USB_VBUS_EN0_PZ1): (MUX UNCLAIMED) tegra-gpio:489
pin 202 (USB_VBUS_EN1_PZ2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 203 (SPI1_SCK_PZ3): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd1 group spi1_sck_pz3
pin 204 (SPI1_MISO_PZ4): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd1 group spi1_miso_pz4
pin 205 (SPI1_MOSI_PZ5): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd1 group spi1_mosi_pz5
pin 206 (SPI1_CS0_PZ6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 207 (SPI1_CS1_PZ7): (MUX UNCLAIMED) (GPIO UNCLAIMED)

[JerryChang]

hello frank2_hsieh

here’s device-tree overlay for 40-pin expansion header, which configure pz3 as input pull-down,
for example,

143 				hdr40-pin23 {
144 					nvidia,pins = "spi1_sck_pz3";
145 					nvidia,function = "spi1";
146 					nvidia,pin-label = "spi1_sck";
147 					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
148 					nvidia,tristate = <TEGRA_PIN_DISABLE>;
149 					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
150 					nvidia,lpdr = <TEGRA_PIN_DISABLE>;
151 				};

could you please check you’re having this overlay included?
you may also have a try to modify the settings to verify the pin configurations,
thanks