Setting Default state of GPIO in Jetson TX2 L4T28.2.1


I tried setting the GPIO9_MOTION_INT GPIO (AA.02) to a default state during the boot up in both tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg file in BCT and my dtbfile.

In BCT file, I changed the pinmux setting to set the gpio as output-low, but I see no chnages after flashing it to the SOM. The pin was still in pull-up state.

pinmux.0x0c303038 = 0x00000004; # can_gpio2_paa2: gpio, pull-down, tristate-disable, input-disable

In DTB file I added the below snippet to pull-down the GPIO.

pinmux@2430000 {
		common {
			can_gpio2_paa2 {
				nvidia,pins = "can_gpio2_paa2";
				nvidia,function = "gpio";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;

But, the GPIO was still in pull-up state.

This GPIO gets configured when I export and change it after bootup.

These changes works good when tried with other GPIOs. Only this GPIO is not configurable. Can you suggest a different method on how to configure this GPIO’s default state as output-low.?

hello akashsekhard,

please refer to Topic 1017764 for some details of can_gpio2_paa2 (Jetson signal GPIO9/MOTION_INT).

Hi JerryChang,

I saw the topic referred by you. The topic discussed about the inability of the pin to set as open-drain configuration. But, our requirement is to pull down the GPIO rather than open-drain. As we mentioned in this thread, we’ve tried the above two methods and it doesn’t help us. Is there any other way to pull down the gpio(can_gpio2_paa2).


hello akashsekhard,

it’s due to GPIO9/MOTION_INT on Jetson-TX2 have LEVEL TRANSLATION on module, they’re unidirection.
hence, GPIO9/MOTION_INT(CAN_GPIO2_PAA2) is input only, and have on module board pull-up, so set SOC internal PD won’t work.
we are updating documents (Jetson-TX2 pinmux spreadsheet) to cover this, sorry for confusion.

Hello JerryChang,

Thanks for the update!

I checked the Jetson_TX2_Module_Datasheet and what you are saying is correct. But, I use similar pins GPIO19/AUD_RST and GPIO8/ALS_PROX_INT along with the GPIO9/MOTION_INT. Both the GPIO19 and GPIO8 are mentioned as input pins and I was able to configure them as output with pull-down. I don’t understand why only GPIO9/MOTION_INT is not able to be configured as output-low. Can you help me out here please.

hello akashsekhard,

it’s due to hardware design, GPIO9/MOTION_INT is not able to configure as normal GPIO.
you may check Jetson-TX2 schematic to check the level shifters for more details.

Hello, JerryChang
Where can we download the Jetson-TX2 schematic? I means the module schematic, not the carrier board schematic, thanks!

hello ericbin,

there’re carrier board schematics you’re able to access through jetson download center, we don’t public release module schematic.

G14/CAN_GPIO2 (GPIO AA.02) is fully configurable as either an output or an input. There is a really strong pull-up (or other logic) on the SoM. The pull-up is strong enough that you cannot override the state by just using the SoC internal pull-down configuration on the pin. However, if you just need it to be in the low state (0) all you need to do is actively drive it low as an output low GPIO. This can be done using the BCT, the kernel DT, or in user space after the system is up.

Here is the patch file that will make G14/CAN_GPIO2 be active low immediately after the MB1 executes:

diff -ur a/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg b/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg
--- a/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg	2019-09-27 12:34:10.678116803 -0500
+++ b/bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg	2019-09-27 12:56:18.763988135 -0500
@@ -75,7 +75,9 @@
 pinmux.0x0c302048 = 0x00000000; # GPIO gpio_sen0_pv0
 pinmux.0x0c2f1c00 = 0x00000001; # CONFIG AA0
 pinmux.0x0c303028 = 0x00000000; # GPIO can_gpio0_paa0
-pinmux.0x0c2f1c40 = 0x00000001; # CONFIG AA2
+pinmux.0x0c2f1c40 = 0x00000003; # CONFIG AA2
+pinmux.0x0c2f1c4c = 0x00000000; # CONTROL AA2
+pinmux.0x0c2f1c50 = 0x00000000; # OUTPUT AA2
 pinmux.0x0c303038 = 0x00000000; # GPIO can_gpio2_paa2
 pinmux.0x0c2f1c60 = 0x00000001; # CONFIG AA3
 pinmux.0x0c303040 = 0x00000000; # GPIO can_gpio3_paa3
@@ -374,7 +376,7 @@
 pinmux.0x0c302070 = 0x00000000; # gpio_sen5_pv5: rsvd0, tristate-disable, input-disable, lpdr-disable
 pinmux.0x0c303028 = 0x00000054; # can_gpio0_paa0: rsvd0, pull-down, tristate-enable, input-enable
 pinmux.0x0c303030 = 0x00000000; # can_gpio1_paa1: rsvd0, tristate-disable, input-disable
-pinmux.0x0c303038 = 0x00000051; # can_gpio2_paa2: rsvd1, tristate-enable, input-enable
+pinmux.0x0c303038 = 0x00000040; # can_gpio2_paa2: rsvd1, tristate-enable, input-enable
 pinmux.0x0c303040 = 0x00000040; # can_gpio3_paa3: rsvd0, tristate-disable, input-enable
 pinmux.0x0c303048 = 0x00000058; # can_gpio4_paa4: rsvd0, pull-up, tristate-enable, input-enable
 pinmux.0x0c303050 = 0x00000040; # can_gpio5_paa5: rsvd0, tristate-disable, input-enable

Note, make sure you are patching/changing the proper .cfg file. You can check that things are working properly by reading the appropriate memory address once you are fully booted:

root@nvtegra:~# devmem2 0x0c303038
/dev/mem opened.
Memory mapped at address 0x7f9d492000.
Read at address  0x0C303038 (0x7f9d492038): 0x00000040

root@nvtegra:~# padctl 0x0c303038
  DRV_TYPE    14:13 0
  SCHMT          12 0
  GPIO_SF_SEL    10 0 (GPIO)
  PBIAS_BUF       9 0
  INPUT           6 1
  TRISTATE        4 0
  PUPD          3:2 0 (NONE)
  PM            1:0 0

Note also that with this configuration properly set the pin will still glitch high for ~250 msec while the BootROM is running, but before the MB1 has a chance to apply the MB1_BCT settings.

can_gpio2_paa2-pinmux-gpio.patch.txt (1.62 KB)

Hi JerryChang,

Is the uni-directional Level Translation you mention actually on the TX2 module itself, or is it on the development carrier board? I noticed that you mentioned that it is on the module, but then referenced the schematics to the dev board.

If I am not using the dev carrier board, is there any problem with making MOTION_INT an output?

No. GPIO9_MOTION_INT/G14 can be used as an output. I’m using it as GPIO AA.02 configured as an output in my design without any issue.