Use PWM8 (13) pin as GPIO

I’m using the latest r36.3 release and I’d like to use the pin 13 of the 40-pins header as GPIO.

Using jetson-io.py it looks like the pin 13 is being used by pwm8 and there is no way to un-select that by using the jetson.io tool. Looking into the DTB it also not clear who is referencing that pin (for sure not pwm8).

I also tried to set that pin function to GPIO3_PR.00 function using the pinmux config tool, but after reflashing with the new pinmux configuration file nothing is changed.

Am I missing anything here?

Put detailed steps or link how you updated pin mux sheet, which file you copied, which file you updated and all

Ok, I’m using Jetson_AGX_Orin_Series_Pinmux_Config_Template_1.9.xlsm file.

I’m modifying the entry for the pin 13, that is PR.00 as in the following picture (I need it as input GPIO):

The Excel macro is generating the pinmux DTSI file as follows:

                       soc_gpio37_pr0 {
                                nvidia,pins = "soc_gpio37_pr0";
                                nvidia,function = "gp";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;

This file has been put in the Linux_for_Tegra/bootloader/generic/BCT directory with the name tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi that is the pinmux file that is being used for my board during the flash procedure, the equivalent GPIO configuration file is placed into Linux_for_Tegra/bootloader.

After re-flashing the board the pin 13 is still seen as set by jetson-io.py:

Is it a dev kit or a customized carrier board you are using?

To verify if your changes are affected you can use the below shown sample fdtdump command on the unit…

Note

To verify whether your changes have taken effect as expected, use fdtdump.

For example, to help you quickly search the output (vim-style search), fdtdump can be used with less.

fdtdump tegra234-p3701-0000+p3737-0005-nv.dtb | less

It is a dev-kit, nothing custom.

You mean Linux_for_Tegra/bootloader/kernel_tegra234-p3737-0000+p3701-0005-nv.dtb ?

I don’t see my changes there but if I understood correctly I should not see any change at all in there because I’m not touching the kernel DTB, I’m changing the MB1 DTB.

At this point I have two questions:

  1. How jetson_io is detecting that I still have the pwm8 function on the pin 13 and why I cannot un-set it?
  2. Given the changes I made to the MB1 DTB, do I need to tweak also the kernel DTB to have the pin 13 configured as GPIO input?

https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#changing-the-pinmux

You can refer this link to dynamically observe or modify gpio register values.
You need to refer TRM to arrive at correct address calculation for that.

Also since you want to set the gpio pin as input, your tristate has to be set to “disabled” I suppose, just cross check again.

Hi ccaione,

Is you issue about PIN13 is configured as pwm8 by default even if your configure it as GPIO3_PR.00 Input/Z in pinmux spreadsheet?

hi @KevinFFF , yes, this is exactly my problem.

It seems you want to use it as Input pin.
Jetson-IO is used to configure the function for the pin and their pinmux. (by adding custom.dtb under /boot)
It would not affect the pin configurations if you don’t run it.

Is there issue that it shows pwm8 in Jetson-IO when you use this pin as input?

The issue is that when I configure pin 13 and 15 as input as follows:

soc_gpio37_pr0 {
    nvidia,pins = "soc_gpio37_pr0";
    nvidia,function = "gp";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_ENABLE>;
    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

soc_gpio39_pn1 {
    nvidia,pins = "soc_gpio39_pn1";
    nvidia,function = "rsvd1";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_ENABLE>;
    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

and I connect the two pins (13 and 15 on the 40-pin headers) to the “Encoder A” and “Encoder B” signals in the following schematics:

as soon as I connect these signals to the 40-pin header, the line is kept UP by Jetson. As soon as I disconnect the pins from the Jetson header, I can see again the signals going up and down when rotating the encoder.

So, there is something wrong in the jetson PIN configuration that is preventing the signals to actually move but I’m failing to see where is the problem.

As comparison this is the signal without the Jetson connected (ranging from 0V to 3V):

This is when the Jetson is connected:

it looks like something on the Jetson side is preventing the signal to go lower than 2V ?

Could you connect the logical analyzer after you connect PIN13/PIN15 to Encoder A/B respectively?

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