Controlling GPIO output pin via gpioset does not work in JP 6.x

Hi all,

I’m trying to use pins from the 40-pin header as output. On a fresh install of both L4T R36.4.3 the following does not change the state of the pin:

gpioset --mode=wait $(gpiofind "PAC.06")=1
gpioset --mode=wait $(gpiofind "PAC.06")=0

The output of gpioinfo looks as expected while the command is running.

The exact same command works as expected on JP 5.1.2 (L4T R35.4.1). In both cases, this is directly after flashing (JP 5.1 requires a sudo apt install gpiod, other than that no changes).

Has anything changed about the default configuration?

Also, I see a “pinmux spreadsheet” being mentioned in the forums, but can’t find it. What is this about?

Looking through the forums a bit further I found this: GPIO issues in Jetpack 6.0 with Linux 36.3

So apparently the issue is that we cannot dynamically switch between input and output anymore and all pins default to input mode. I also found the pinmux spreadsheet in the meantime, but it only mentions Jetson AGX Orin, not Orin Nano. Is it still applicable? More concretely: What exactly do I have to do to configure pins as output pins on Jetson Orin Nano with JP 6.x?

Alright, making good progress and documenting my findings now here in case others come across this (and also for my future self).

Indeed the default mode of the pins has changed and most default to “input only” now. To use them as output, you need to adjust the DTB. Alternatively, you can write to some register. That’s what worked for me now.

Information on how to change the DTB is here: Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide 1 documentation

This page tells you to search for “Orin Series Pinmux” in the Jetson Download Center. However, doing so yields only one result, which is the AGX Orin one, not Nano! Searching for “nano series pinmux” gives the correct link. Note that a search just for “pin” gives a couple of pinmux results, but not the Orin Nano one. That explains why I had such a hard time finding that spreadsheet. Here is the complete link: https://developer.nvidia.com/downloads/jetson-orin-nx-and-orin-nano-series-pinmux-config-template

From there, you need to get hold of a copy of Microsoft Excel to use the spreadsheet, configure the pins that are supposed to be used as output, generate the dtsi files, use those to generate some more files, and eventually flash the result to the Jetson. Since I don’t have access to Microsoft Excel, I didn’t try that yet, but I suppose it would work.

Alternatively, you can write to some control register at runtime. This is “explained” here

Without this example, I would have had a very hard time finding out the address. “TRM” in point A is the Technical Reference Manual, which is then linked in point D. It’s the exact same document.

So once I had the address, I was able to read the value using busybox devmem <address>. It was always giving me 0x0000005A. The documentation says that for an input, bits 4 and 6 are set, which they indeed are in 0x0000005A. Flipping those, I get 0x0000000A. Once I had written that value to the register, I was able to use the pin as output!

Now what’s left is finding the addresses of the other pins that I need and put the busybox devmem commands in some startup script.

I agree with @bremen_matt and @tteuber in the aforementioned thread that changing the default behaviour without explicit note or a migration guide is not exactly customer friendly. On top of that we have @DaveYYY’s very inappropriate tone. Nvidia might be ahead of the competition at the moment, but once other vendors catch up, the way you treat customers will make a difference. The documentation is very much overwhelming, partly incomplete, partly outdated. If then somebody with “nvidia” next to their name calls people “dude” and treats them like little school boys that failed to read the assignment correctly, at least I will consider alternatives. That spreadsheet only working with Excel on Windows really is the icing on the cake here!

1 Like

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.

Hi ahans123,

Thanks for pointing out the GPIO control issue in JP6.

AGX Orin and Orin Nano/NX are from similar Orin platform(T234), but they are different modules and we have separate guide for them.
It is caused from that the adaptation guide you were referring is for AGX Orin( Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide 1 documentation)
If you are using Orin Nano, please refer to Jetson Orin NX and Nano Series — NVIDIA Jetson Linux Developer Guide 1 documentation.

Yes, TRM is Technical Reference Manual and you can download it from Jetson Download Center.
For the PADCTL address, you can also refer to Calculating/Getting register adresses of gpio pins - #7 by jost38

Let me take an example for PAC.06(SOC_GPIO59).
Once you find its pinmux address(0x02448030 = Base+offset = 0x02448000+0x30 ), you can run sudo busybox devmem 0x02448030 to get its value.
Bit 0:1 → Functions
Bit 2:3 → PULL
Bit 4 → TRISTATE
Bit 6 → ENABLE Input
Bit 10 → SFIO/GPIO
Above information should be included in TRM.

Sorry for the inconvenience and inappropriate response from us.
The most of pins are configured as GPIO Input by default, but you can configure them as Bi-directional in pinmux spreadsheet instead. We’ve also mentioned it in developer guide as following:

However, we have a known issue in both JP6.0(R36.3.0) and JP6.1(R36.4.0), which has been fixed in JP6.2(R36.4.3).

About pinmux spreadsheet only works with Excel on Windows, it is caused that the macro features were designed there.
Actually, you can also modify the pinmux dtsi file directly if you are familiar with those attributes.
Normally, we would just suggest user using the pinmux spreasheet in case some attributes were not configured correctly.

Moreover, we’ve also discussed GPIO control issue in JP6 with internal.
We collected many feedbacks from forum.
The good news is that it seems Jetson-IO would support to configure pins on 40-pins header to use them as GPIO or specific functions in the next release.