I am working on NVIDIA AGX XAVIER machine and completely new to this. I have gone through the documentations as well as forums regarding establishing the can connection. I am using Jetpack 5.1 version and ubuntu version18.04. I tried the loopback test and it works fine. But it doesn’t work in normal mode. Whenever i transmit data packets using cansend and candump from can0 to can1,the transmitting side bus-state always changes to “BUS-OFF” state.Checked the signal using oscilloscope as well as logic analyzer but couldn’t detect any signal.
Tried changing the pll_aon as parent clock source(Clocks — Jetson Linux<br/>Developer Guide 34.1 documentation) ,made changes in the bootloader( tegra194-a02-bpmp-p2888-a04.dtb) and kernel( tegra194-p2888-0001-p2822-0000.dtb) in the host machine and flashed them into the agx xavier machine using the following commands
sudo ./flash.sh -k kernel-dtb jetson-agx-xavier-devkit mmcblk0p1*
The commands ran without any error but the changes aren’t reflected. Still the parent-clock remains the same “osc”.
Hi Kevin,
I am using the Devkit for the AGX Xavier.
For connecting the controllers , we used 2 SN65HVD230 transceivers just as mentioned in the documentation .i attached the image of the connections below.
Could you just refer to the instruction from developer guide to configure can bus?
$ ip link set can0 up type can bitrate 500000 dbitrate 1000000 berr-reporting on fd on
$ ip link set can1 up type can bitrate 500000 dbitrate 1000000 berr-reporting on fd on
I think you don’t need to change the parent clock for this test.
Goal : Make CAN Bus work in NVIDIA AGX ORIN and XAVIER with Jetpack 5.1
Currently we are trying on AGX XAVIER. Degraded the jetpack version to 4.6 based on the forums suggestions that CAN works fine. But still the issue persists(couldn’t detect any signal from logic analyzer ).I also attached a pdf below stating the procedure we followed for changing pllaon . PLLAON_clock_source.pdf (1.9 MB)
With or without changing the parent clock we want to make the CAN work with default configurations .
Kindly suggest the connection based on the below document? Connection_diagram.pdf (44.3 KB)
The below is the output you requested for
Also is the Jetpack version 5.1 tested for CAN communication?
We had been making the connections in the same way from the start .
Could you share the steps of how to
is it possible to get an image of the physical connections of controller and transceiver you set?
Also could you explain the procedure you have followed on establishing the connection between the two controllers?
Hello Kevin, thanks for your prompt and right time support. As we are in process of critically bringing up the CAN (alteast a minimal external communication working), I request you to kindly provide the below at the earliest possible;
CAN controller details and datasheet (if not available in open links). This will help us to debug the driver.
Possibly please share the current CAN driver source(wrt Jetpack 5.1.1) and building procedure.
Also please share the procedure for open-source CAN driver building for ORIN AGX/XAVIER AGX boards.
Any direction to make the CAN up and running in Jetpack 5.1.1 . We were referring the online guide from Jetson sites/forums but it is not working(No activity or signals in the CAN0/1 Tx Rx).We tried to glow an LED at Expansion Header Pin 29,31,33,37 and it is glowing even after pinmux configuration. We believe still GPIO is active though we expect it to be as CAN Tx Rx. Kindly suggest.