CAN controller not transmitting signal inAGX XAVIER

I am working on NVIDIA AGX XAVIER machine and completely new to this. I have gone through the documentations as well as forums regarding establishing the can connection. I am using Jetpack 5.1 version and ubuntu version18.04. I tried the loopback test and it works fine. But it doesn’t work in normal mode. Whenever i transmit data packets using cansend and candump from can0 to can1,the transmitting side bus-state always changes to “BUS-OFF” state.Checked the signal using oscilloscope as well as logic analyzer but couldn’t detect any signal.
Tried changing the pll_aon as parent clock source(Clocks — Jetson Linux<br/>Developer Guide 34.1 documentation) ,made changes in the bootloader( tegra194-a02-bpmp-p2888-a04.dtb) and kernel( tegra194-p2888-0001-p2822-0000.dtb) in the host machine and flashed them into the agx xavier machine using the following commands

  • sudo ./ -k bpmp-fw-dtb jetson-agx-xavier-devkit mmcblk0p1*
  • sudo ./ -k kernel-dtb jetson-agx-xavier-devkit mmcblk0p1*
    The commands ran without any error but the changes aren’t reflected. Still the parent-clock remains the same “osc”.


Hi billakurthi.sivasai,

Are you using the devkit or custom board for AGX Xavier?

It is internal loopback test, and it should work fine w/o any external connection.

How do you connect your CAN0 to CAN1?
You have to connect them through 2 CAN transceivers as the instruction mentioned.

Hi Kevin,
I am using the Devkit for the AGX Xavier.

For connecting the controllers , we used 2 SN65HVD230 transceivers just as mentioned in the documentation .i attached the image of the connections below.

We tried to change the pllaon as parent clock and it worked but still couldn’t observe any data transmission from can0 to can1.

Do you think the change of parent clock from osc to pllaon is a better idea?

Have you used Jetson-IO to configure the pinmux for both CAN0 and CAN1?

Please share the result of the following command on your board.

$sudo busybox devmem 0x0c303018
$sudo busybox devmem 0x0c303010
$sudo busybox devmem 0x0c303008
$sudo busybox devmem 0x0c303000

Could you just refer to the instruction from developer guide to configure can bus?

$ ip link set can0 up type can bitrate 500000 dbitrate 1000000 berr-reporting on fd on
$ ip link set can1 up type can bitrate 500000 dbitrate 1000000 berr-reporting on fd on

I think you don’t need to change the parent clock for this test.

Thanks Kevin,

Goal : Make CAN Bus work in NVIDIA AGX ORIN and XAVIER with Jetpack 5.1

  1. Currently we are trying on AGX XAVIER. Degraded the jetpack version to 4.6 based on the forums suggestions that CAN works fine. But still the issue persists(couldn’t detect any signal from logic analyzer ).I also attached a pdf below stating the procedure we followed for changing pllaon .
    PLLAON_clock_source.pdf (1.9 MB)

  2. With or without changing the parent clock we want to make the CAN work with default configurations .

  3. Kindly suggest the connection based on the below document?
    Connection_diagram.pdf (44.3 KB)

  4. The below is the output you requested for

  5. Also is the Jetpack version 5.1 tested for CAN communication?

Please connect CAN0-TX to CAN-Transceiver-TX, CAN0-RX to CAN-Transceiver-RX, so does CAN1.

We had been making the connections in the same way from the start .
Could you share the steps of how to
is it possible to get an image of the physical connections of controller and transceiver you set?
Also could you explain the procedure you have followed on establishing the connection between the two controllers?

I connect them as following.

Could you get the same WaveShare SN65HVD230 CAN board CAN transceiver as the developer guide suggested to verify?

Currently we don’t have it,we will try with it and inform you the result.

Hello Kevin, thanks for your prompt and right time support. As we are in process of critically bringing up the CAN (alteast a minimal external communication working), I request you to kindly provide the below at the earliest possible;

  1. CAN controller details and datasheet (if not available in open links). This will help us to debug the driver.

    • Possibly please share the current CAN driver source(wrt Jetpack 5.1.1) and building procedure.
    • Also please share the procedure for open-source CAN driver building for ORIN AGX/XAVIER AGX boards.
  2. Any direction to make the CAN up and running in Jetpack 5.1.1 . We were referring the online guide from Jetson sites/forums but it is not working(No activity or signals in the CAN0/1 Tx Rx).We tried to glow an LED at Expansion Header Pin 29,31,33,37 and it is glowing even after pinmux configuration. We believe still GPIO is active though we expect it to be as CAN Tx Rx. Kindly suggest.

Thanks and appreciate your good responses.

With Regards

Hi billakurthi.sivasai,

You could refer to the following thread about our verification for CAN bus on AGX Xavier devkit with latest R35.3.1.
Jetson AGX Xavier Developer Kit CAN commmunication error - #8 by KevinFFF

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