CSI-2 Adv7280 compatibility with Jetson TX1

hey forum!
i want to input analog pal video to an Analog device Adv7280 and get CSI-2 digital video that i want to acquire into the jetson TX-1 over its CSI-2 interface…i know its doable on the jetson tx1…the question is how?..any help will be highly appreciated…
best regards
Ali

I was reviewing http://www.analog.com/media/en/technical-documentation/user-guides/ADV7280_7281_7282_7283_UG-637.pdf and at a glance the ADV7280’s CSI-2 single-lane interface appears electrically compatible with JTX1 module. As with other CSI sensors, it will potentially require software driver customizations specific to the ADV7280. I was looking at the eval board which looks to bring the CSI signals out via SMA connector:

For testing with JTX1 you would likely need to fabricate an adapter board to connect the SMA’s to the devkit. Have you reviewed our schematics and design files for the camera module included in the devkit? http://developer.nvidia.com/embedded/dlc/jetson-tx1-developer-kit-camera-module-schematic-and-layout-files

Thankyou but before i take a look at the schematics …i am more interested in the software compatibility of adv7280 with linux on tx1…i ve no clue here
best regards
ali

OK, for driver examples, check out http://developer.download.nvidia.com/embedded/L4T/r23_Release_v1.0/source/kernel_src.tbz2
and look into the kernels/drivers/media/i2c/soc_camera directory

ADV7280 support was added to the ADV7180 kernel driver in the following two commits:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/media/i2c/adv7180.c?id=b37135e395c37a8d63defafcb567d55220a672f0
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/media/i2c/adv7180.c?id=bf7dcb8067ed5c3b40768b071d93bd7676e36620

You’d probably have a bit of work to backport them to the 3.10 base kernel and then write a soc_camera driver to support setting up the CSI lanes on the TX1 properly. Finally you’d have to describe the 7280s connection to the I2C interfaces in the devicetree:
https://www.kernel.org/doc/Documentation/i2c/instantiating-devices

7180 can input pal and output 8 bit or 16 bit video data…can i make use of the adv7180 here and import that pixel information as a frame in the jetson tx1?..i just want to access analog video into jetson…if adv7180 is already working in linux i will prefer it over 7280 since i ve zero experience in writing drivers for linux…please advise
best regards
ali

No, the 7180 will not work out of the box and includes a parallel digital interface so it would be more tricky to integrate (I don’t believe the TX1 ISP has a parallel interface)

If all you want is to digitize analog video why don’t you look at USB solutions? Devices based on the STK1160 are popular with hobbyists using ARM devices and the kernel module should be easy to build.

I have heard about easycap…ok…has anybody tried to capture 25 fps pal video 720x576 on jetson using easycap before?..how was the performance?
Best regards
ali

HI Everyone

The MIPI i/F of the ADV7280M is single lane, but can Jetson_TX1 support ?

best regard.

Hi nVIDIA staff

No one answers.
I will change my question.

Q1> MIPI_CSi2 i / F block of Tegra X1 / X2 is a hardware specification that can support 1 lane device? (Register configuration etc.)

Q2> Is the function to acquire normal images from 1 lane device with the current Jetson Linux / JetPack installed?

best regard.

Hi BlueYatagarasu

  1. Yes, TX1 can support 1x, 2x, 4x use case.
  2. You need to implement the sensor driver for this chip. You can download the document to read the “Sensor Driver Programming Guide” chapter first.

Hi. ShaneCCC

Thank you for your answer.

Can you understand that you can successfully capture images even when x1, x2, x4 devices are connected in board design of 4 lanes / 2 cameras?

For 2 lanes / 6 cameras it will be images of x1, x2 devices.

Which package contains the “Sensor Driver Programming Guide” that was mentioned?

dest regards.

You can check the TX1 TRM for the csi support
http://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual

Post the document link
http://developer.nvidia.com/embedded/dlc/l4t-documentation-24-2-1

Hi. ShaneCCC

Thank you for your answer.
As I understood the location of the description, I will read it first.

best regards.

Hi. ShaneCCC

I have read the specified document.

I understood as follows, is it correct?

· 2 lane / 6 pin configuration of the camera is possible.
In this case, it can support 1 lane camera and 2 lane camera.
· Pin configuration of 4 lanes / 2 cameras is possible.
In this case, it can support 1 lane camera, 2 lane camera, 4 lane camera.

We are planning to design a board with “4 lanes / 2 cameras” pin configuration and want to be able to change the camera to be connected.

The following is a question.
The 4 lane camera was able to connect three (CSI - A / B / C).
2 For camera connection, is it OK if you connect to CSI-A and CSI-B and CSI-C do free terminal processing?

best regards.

Hi. ShaneCCC (resend)

I have read the specified document.

I understood as follows, is it correct?

· Pin configuration of “2 lanes / 6 cameras” is possible.
In this case, it can support 1 lane camera and 2 lane camera.
· Pin configuration of “4 lanes / 2 cameras” is possible.
In this case, it can support 1 lane camera, 2 lane camera, 4 lane camera.

We are planning to design a board with “4 lanes / 2 cameras” pin configuration and want to be able to change the camera to be connected.

The following is a question.
The 4 lane camera was able to connect three (CSI - A / B / C).
2 For camera connection, is it OK if you connect to CSI-A and CSI-B and CSI-C do free terminal processing?

@BuleYatagarasu
What’s terminal processing? 4 lanes means you can use CSIA/CSIB, CSIC/CSID or CSIE/CSIF,
And your understanding is correct for the pin configuration of “2 lanes / 6 cameras” and “4 lanes / 2 cameras”

Hi. ShaneCCC

Sorry for the poor English.
It seems that the meaning did not pass.

What’s terminal processing?
I was going to process unused pins.
In the “2 Camera / 4 Lane” configuration, will free terminals occur?
(register termination)

I plan to use “4-Lanes Each / 1 of 3 Cameras, 2 of 3 Cameras” described in Table 49 (P.44) of “Jetson TX1 OEM Product Design Guide”.

Taking the camera 1 as an example, the connection of the MIPI-CSI 2 signal line
·CLK -> CSI_0_CLK
· Lane 0 -> CSI_0_D[0]
· Lane 1 -> CSI_0_D[1]
· Lane 2 -> CSI_1_D[0]
· Lane 3 -> CSI_1_D[1]

Correct?

best regard.

It is correct for 4-lane CSI.

·CLK -> CSI_0_CLK
· Lane 0 -> CSI_0_D[0]
· Lane 1 -> CSI_0_D[1]
· Lane 2 -> CSI_1_D[0]
· Lane 3 -> CSI_1_D[1]

Hi. ShaneCCC

Thanks for your comment.

With this, you can design the board with confidence.
Connect the ADV7280M of 1 lane device as follows.

CLK -> CSI_0_CLK -> ADV7280M : CLK (MIPI)
Lane 0 -> CSI_0_D[0] -> ADV7280M : D0 (MIPI)
Lane 1 -> CSI_0_D[1] -> (not used)
Lane 2 -> CSI_1_D[0] -> (not used)
Lane 3 -> CSI_1_D[1] -> (not used)

If you write even the driver, it will work without problems.

best regards.