cuBB E2E multiple cell test fail

Accelerated Computing Aerial Forum
,
1

Hi

I am currently running the 25-1-cuBB cuBB E2E test and encountered some issues.
When I run the F08 2C 59c test, the ru-emulator console shows DL Core 7 handling 1 flows, and it should normally start displaying the console logs for RU cell throughput.

However, after about one second, it shows Finalizing..., then directly proceeds to termination and finally shows “abort”, as shown as below.

->$ sudo ./ru_emulator F08 2C 59c
12:18:00.359274 CON 553 0 [NVLOG.CPP] Using /opt/nvidia/cuBB/cuPHY/nvlog/config/nvlog_config.yaml for nvlog configuration
12:18:00.366206 CON 553 0 [NVLOG.CPP] Output log file path /tmp/ru.log
12:18:00.366398 CON 553 0 [RU.PARSER] Run ./ru_emulator launch_pattern_F08_2C_59c.yaml channel_mask 0
12:18:00.366401 CON 553 0 [RU] PUSCH enabled!
12:18:00.366402 CON 553 0 [RU] PUCCH enabled!
12:18:00.366402 CON 553 0 [RU] PRACH enabled!
12:18:00.366402 CON 553 0 [RU] SRS enabled!
12:18:00.366403 CON 553 0 [RU.PARSER] Enabled channels: PUSCH PDSCH PDCCH_UL PDCCH_DL PBCH PUCCH PRACH CSI_RS SRS DL_BFW UL_BFW | channel_mask=0x7FF
12:18:00.366415 CON 553 0 [RU] Config file: /opt/nvidia/cuBB/cuPHY-CP/ru-emulator/config/config.yaml
12:18:00.366948 CON 553 0 [RU] Keeping default num_slots_ul = 25
12:18:00.366958 CON 553 0 [RU] Keeping default num_slots_dl = 100
12:18:00.366963 CON 553 0 [RU] Keeping default timer_level = 0
12:18:00.366966 CON 553 0 [RU] Keeping default timer_offset_us = -20
12:18:00.366969 CON 553 0 [RU] Keeping default symbol_offset_us = 0
12:18:00.366972 CON 553 0 [RU] Keeping default send_slot = 0
12:18:00.366975 CON 553 0 [RU] Keeping default c_interval = 0
12:18:00.366978 CON 553 0 [RU] Keeping default c_plane_per_symbol = 1
12:18:00.366980 CON 553 0 [RU] Keeping default prach_c_plane_per_symbol = 0
12:18:00.366985 CON 553 0 [RU] Keeping default ul_enabled = 1
12:18:00.366988 CON 553 0 [RU] Keeping default prach_enabled = 1
12:18:00.366991 CON 553 0 [RU] Keeping default srs_enabled = 1
12:18:00.366994 CON 553 0 [RU] Keeping default dl_enabled = 1
12:18:00.366997 CON 553 0 [RU] Keeping default forever = 1
12:18:00.367002 CON 553 0 [RU] Keeping default drop_packet_every_ten_secs = 0
12:18:00.367005 CON 553 0 [RU] Keeping default split_srs_txq = 1
12:18:00.367024 CON 553 0 [RU] Launch pattern file: /opt/nvidia/cuBB/testVectors/multi-cell/launch_pattern_F08_2C_59c.yaml
EAL: Detected CPU lcores: 16
EAL: Detected NUMA nodes: 1
EAL: Detected shared linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/ru_emulator/mp_socket
EAL: Selected IOVA mode 'PA'
EAL: VFIO support initialized
12:18:00.890402 CON 553 0 [RU.PARSER] Launch Pattern v2 preprocessing finished in 0.52s
12:18:00.891538 CON 553 0 [RU.PARSER] Launch Pattern parsing finished in 0.0011s
12:18:00.891556 CON 553 0 [RU] YAML invalid key: INIT, Init launch pattern missing, using only normal launch pattern
EAL: Probe PCI driver: mlx5_pci (15b3:a2dc) device: 0000:c3:00.0 (socket 0)
12:18:01.731462 CON 553 0 [RU] Forever is enabled, ignoring num_slots_ul and num_slots_dl
12:18:01.731463 CON 553 0 [RU] No SRS TVs provided, disabling SRS channel
12:18:01.731463 CON 553 0 [RU] No BFW DL TVs provided, disabling BFW DL Validation

12:18:01.731463 CON 553 0 [RU] No BFW UL TVs provided, disabling BFW UL Validation

12:18:02.313177 CON 553 0 [RU] Loaded PUSCH TVs in 0.58s
12:18:02.457604 CON 553 0 [RU] Loaded PRACH TVs in 0.14s
12:18:03.820236 CON 553 0 [RU] Loaded PUCCH TVs in 1.36s
12:18:03.820237 CON 553 0 [RU] Loaded SRS TVs in 0.00s
12:18:06.605959 CON 553 0 [RU] Load PDSCH TVs compute 2.78s load qams 0.00s
12:18:06.605960 CON 553 0 [RU] Loaded PDSCH TVs in 2.79s
12:18:06.637413 CON 553 0 [RU] Loaded PBCH TVs in 0.03s
12:18:06.902965 CON 553 0 [RU] Load PDCCH TVs compute 0.26s load qams 0.00s
12:18:06.902966 CON 553 0 [RU] Loaded PDCCH_UL TVs in 0.27s
12:18:07.168445 CON 553 0 [RU] Load PDCCH TVs compute 0.26s load qams 0.00s
12:18:07.168446 CON 553 0 [RU] Loaded PDCCH_DL TVs in 0.27s
12:18:07.333210 CON 553 0 [RU] Loaded CSIRS TVs in 0.16s
12:18:07.340223 CON 553 0 [RU.PARSER] ================================================================================================
12:18:07.340224 CON 553 0 [RU.PARSER]   Config file used: /opt/nvidia/cuBB/cuPHY-CP/ru-emulator/config/config.yaml
12:18:07.340224 CON 553 0 [RU.PARSER]   Launch Pattern file used: /opt/nvidia/cuBB/testVectors/multi-cell/launch_pattern_F08_2C_59c.yaml
12:18:07.340224 CON 553 0 [RU.PARSER] ================================================================================================
12:18:07.348740 CON 570 0 [RU] Thread ul_core0 initialized fmtlog
12:18:07.348849 CON 571 0 [RU] Thread ul_core1 initialized fmtlog
12:18:07.348878 CON 573 0 [RU] Thread dl_proc-1 initialized fmtlog
12:18:07.348880 CON 573 0 [RU] DL Core 1 handling 1 flows
12:18:07.348883 CON 572 0 [RU] Thread dl_proc-0 initialized fmtlog
12:18:07.348883 CON 572 0 [RU] DL Core 0 handling 1 flows
12:18:07.349026 CON 575 0 [RU] Thread dl_proc-3 initialized fmtlog
12:18:07.349026 CON 575 0 [RU] DL Core 3 handling 1 flows
12:18:07.349057 CON 574 0 [RU] Thread dl_proc-2 initialized fmtlog
12:18:07.349057 CON 574 0 [RU] DL Core 2 handling 1 flows
12:18:07.349111 CON 576 0 [RU] Thread dl_proc-4 initialized fmtlog
12:18:07.349111 CON 576 0 [RU] DL Core 4 handling 1 flows
12:18:07.349244 CON 577 0 [RU] Thread dl_proc-5 initialized fmtlog
12:18:07.349244 CON 577 0 [RU] DL Core 5 handling 1 flows
12:18:07.349609 CON 578 0 [RU] Thread dl_proc-6 initialized fmtlog
12:18:07.349610 CON 578 0 [RU] DL Core 6 handling 1 flows
12:18:07.349674 CON 579 0 [RU] Thread dl_proc-7 initialized fmtlog
12:18:07.349674 CON 579 0 [RU] DL Core 7 handling 1 flows
12:18:08.341529 CON 553 0 [RU] Finalizing...
12:18:08.341606 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341619 CON 553 0 [FH.PACKET_SUMMARY] slot,cell_0_early,cell_0_ontime,cell_0_late,cell_1_early,cell_1_ontime,cell_1_late,
12:18:08.341621 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 4 | 0,208,0 | 0,208,0 |
12:18:08.341621 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 5 | 0,312,0 | 0,312,0 |
12:18:08.341622 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 14 | 0,200,0 | 0,200,0 |
12:18:08.341622 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 15 | 0,300,0 | 0,300,0 |
12:18:08.341623 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 24 | 0,208,0 | 0,208,0 |
12:18:08.341623 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 25 | 0,312,0 | 0,312,0 |
12:18:08.341624 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 34 | 0,200,0 | 0,200,0 |
12:18:08.341624 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 35 | 0,300,0 | 0,300,0 |
12:18:08.341624 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 44 | 0,200,0 | 0,200,0 |
12:18:08.341625 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 45 | 0,300,0 | 0,300,0 |
12:18:08.341625 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 54 | 0,192,0 | 0,192,0 |
12:18:08.341625 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 55 | 0,288,0 | 0,288,0 |
12:18:08.341626 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 64 | 0,200,0 | 0,200,0 |
12:18:08.341626 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 65 | 0,300,0 | 0,300,0 |
12:18:08.341627 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 74 | 0,200,0 | 0,200,0 |
12:18:08.341627 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 75 | 0,300,0 | 0,300,0 |
12:18:08.341633 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 4 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341634 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 5 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341635 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 14 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341637 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 15 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341638 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 24 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341639 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 25 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341640 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 34 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341641 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 35 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341642 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 44 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341643 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 45 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341644 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 54 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341645 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 55 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341646 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 64 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341647 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 65 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341648 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 74 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341650 CON 553 0 [FH.PACKET_SUMMARY] ULC Slot 75 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341780 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341781 CON 553 0 [FH.PACKET_SUMMARY] slot,cell_0_early,cell_0_ontime,cell_0_late,cell_1_early,cell_1_ontime,cell_1_late,
12:18:08.341782 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 0 | 0,1600,0 | 0,1600,0 |
12:18:08.341783 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 1 | 0,1600,0 | 0,1600,0 |
12:18:08.341783 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 2 | 0,1600,0 | 0,1600,0 |
12:18:08.341783 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 3 | 0,728,0 | 0,728,0 |
12:18:08.341784 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 6 | 0,1508,0 | 0,1508,0 |
12:18:08.341784 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 7 | 0,1508,0 | 0,1508,0 |
12:18:08.341784 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 8 | 0,1612,0 | 0,1612,0 |
12:18:08.341785 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 9 | 0,1508,0 | 0,1508,0 |
12:18:08.341785 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 10 | 0,1612,0 | 0,1612,0 |
12:18:08.341785 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 11 | 0,1508,0 | 0,1508,0 |
12:18:08.341786 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 12 | 0,1456,0 | 0,1456,0 |
12:18:08.341786 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 13 | 0,624,0 | 0,624,0 |
12:18:08.341786 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 16 | 0,1612,0 | 0,1612,0 |
12:18:08.341787 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 17 | 0,1508,0 | 0,1508,0 |
12:18:08.341787 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 18 | 0,1456,0 | 0,1456,0 |
12:18:08.341787 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 19 | 0,1456,0 | 0,1456,0 |
12:18:08.341788 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 20 | 0,1456,0 | 0,1456,0 |
12:18:08.341788 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 21 | 0,1456,0 | 0,1456,0 |
12:18:08.341788 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 22 | 0,1456,0 | 0,1456,0 |
12:18:08.341789 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 23 | 0,624,0 | 0,624,0 |
12:18:08.341789 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 26 | 0,1612,0 | 0,1612,0 |
12:18:08.341789 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 27 | 0,1508,0 | 0,1508,0 |
12:18:08.341789 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 28 | 0,1612,0 | 0,1612,0 |
12:18:08.341790 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 29 | 0,1508,0 | 0,1508,0 |
12:18:08.341790 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 30 | 0,1612,0 | 0,1612,0 |
12:18:08.341790 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 31 | 0,1508,0 | 0,1508,0 |
12:18:08.341791 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 32 | 0,1456,0 | 0,1456,0 |
12:18:08.341791 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 33 | 0,624,0 | 0,624,0 |
12:18:08.341791 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 36 | 0,1456,0 | 0,1456,0 |
12:18:08.341792 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 37 | 0,1456,0 | 0,1456,0 |
12:18:08.341792 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 38 | 0,1456,0 | 0,1456,0 |
12:18:08.341792 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 39 | 0,1456,0 | 0,1456,0 |
12:18:08.341793 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 40 | 0,1664,0 | 0,1664,0 |
12:18:08.341793 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 41 | 0,1664,0 | 0,1664,0 |
12:18:08.341793 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 42 | 0,1664,0 | 0,1664,0 |
12:18:08.341794 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 43 | 0,728,0 | 0,728,0 |
12:18:08.341794 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 46 | 0,1550,0 | 0,1550,0 |
12:18:08.341795 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 47 | 0,1450,0 | 0,1450,0 |
12:18:08.341795 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 48 | 0,1450,0 | 0,1450,0 |
12:18:08.341795 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 49 | 0,1410,0 | 0,1410,0 |
12:18:08.341796 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 50 | 0,1392,0 | 0,1392,0 |
12:18:08.341796 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 51 | 0,1392,0 | 0,1392,0 |
12:18:08.341796 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 52 | 0,1344,0 | 0,1344,0 |
12:18:08.341797 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 53 | 0,576,0 | 0,576,0 |
12:18:08.341797 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 56 | 0,1392,0 | 0,1392,0 |
12:18:08.341797 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 57 | 0,1392,0 | 0,1392,0 |
12:18:08.341798 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 58 | 0,1348,0 | 0,1344,0 |
12:18:08.341798 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 59 | 0,1400,0 | 0,1392,0 |
12:18:08.341798 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 60 | 0,1344,0 | 0,1356,0 |
12:18:08.341798 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 61 | 0,1392,0 | 0,1392,0 |
12:18:08.341799 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 62 | 0,1400,0 | 0,1400,0 |
12:18:08.341799 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 63 | 0,600,0 | 0,600,0 |
12:18:08.341799 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 66 | 0,1450,0 | 0,1450,0 |
12:18:08.341800 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 67 | 0,1450,0 | 0,1450,0 |
12:18:08.341800 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 68 | 0,1450,0 | 0,1450,0 |
12:18:08.341800 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 69 | 0,1450,0 | 0,1450,0 |
12:18:08.341801 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 70 | 0,1450,0 | 0,1450,0 |
12:18:08.341801 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 71 | 0,1450,0 | 0,1450,0 |
12:18:08.341801 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 72 | 0,1400,0 | 0,1400,0 |
12:18:08.341802 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 73 | 0,600,0 | 0,600,0 |
12:18:08.341802 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 76 | 0,1400,0 | 0,1400,0 |
12:18:08.341802 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 77 | 0,1400,0 | 0,1400,0 |
12:18:08.341802 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 78 | 0,1400,0 | 0,1400,0 |
12:18:08.341803 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 79 | 0,1400,0 | 0,1400,0 |
12:18:08.341805 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 0 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341806 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 1 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341807 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 2 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341808 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 3 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341809 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 6 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341811 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 7 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341812 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 8 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341813 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 9 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341814 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 10 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341815 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 11 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341816 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 12 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341817 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 13 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341818 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 16 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341819 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 17 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341820 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 18 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341821 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 19 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341822 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 20 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341823 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 21 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341824 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 22 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341826 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 23 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341827 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 26 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341828 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 27 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341829 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 28 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341830 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 29 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341831 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 30 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341832 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 31 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341833 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 32 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341834 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 33 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341835 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 36 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341836 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 37 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341837 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 38 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341838 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 39 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341839 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 40 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341840 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 41 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341841 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 42 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341843 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 43 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341844 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 46 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341845 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 47 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341846 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 48 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341847 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 49 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341848 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 50 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341849 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 51 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341850 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 52 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341851 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 53 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341852 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 56 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341853 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 57 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341854 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 58 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341855 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 59 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341857 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 60 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341858 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 61 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341859 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 62 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341860 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 63 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341861 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 66 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341862 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 67 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341863 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 68 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341864 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 69 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341865 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 70 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341866 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 71 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341867 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 72 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341868 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 73 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341869 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 76 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341870 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 77 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341871 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 78 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341872 CON 553 0 [FH.PACKET_SUMMARY] DLC Slot 79 | 0.00,100.00,0.00 | 0.00,100.00,0.00 |
12:18:08.341928 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341929 CON 553 0 [FH.PACKET_SUMMARY] slot,cell_0_early,cell_0_ontime,cell_0_late,cell_1_early,cell_1_ontime,cell_1_late,
12:18:08.341956 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341957 CON 553 0 [RU] | Total Cells                    |      Cell 0 |      Cell 1 |
12:18:08.341958 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341959 CON 553 0 [RU] | UL_C_PLANE slots received      |         403 |         403 |
12:18:08.341960 CON 553 0 [RU] | DL_C_PLANE slots received      |        1626 |        1626 |
12:18:08.341960 CON 553 0 [RU] | DL_U_PLANE slots received      |        1598 |        1600 |
12:18:08.341961 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341962 CON 553 0 [RU] | GOOD PBCH slots processed      |         201 |         204 |
12:18:08.341963 CON 553 0 [RU] | BAD PBCH slots processed       |           0 |           0 |
12:18:08.341964 CON 553 0 [RU] | TOT PBCH slots processed       |         201 |         204 |
12:18:08.341964 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341965 CON 553 0 [RU] | GOOD PDSCH slots processed     |        1593 |        1593 |
12:18:08.341965 CON 553 0 [RU] | BAD PDSCH slots processed      |           0 |           0 |
12:18:08.341965 CON 553 0 [RU] | TOT PDSCH slots processed      |        1593 |        1593 |
12:18:08.341966 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341966 CON 553 0 [RU] | GOOD PDCCH_UL slots processed  |        1596 |        1598 |
12:18:08.341967 CON 553 0 [RU] | BAD PDCCH_UL slots processed   |           0 |           0 |
12:18:08.341967 CON 553 0 [RU] | TOT PDCCH_UL slots processed   |        1596 |        1598 |
12:18:08.341967 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341968 CON 553 0 [RU] | GOOD PDCCH_DL slots processed  |        1596 |        1598 |
12:18:08.341968 CON 553 0 [RU] | BAD PDCCH_DL slots processed   |           0 |           0 |
12:18:08.341969 CON 553 0 [RU] | TOT PDCCH_DL slots processed   |        1596 |        1598 |
12:18:08.341985 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341986 CON 553 0 [RU] | GOOD CSI_RS slots processed    |         693 |         693 |
12:18:08.341986 CON 553 0 [RU] | BAD CSI_RS slots processed     |           0 |           0 |
12:18:08.341987 CON 553 0 [RU] | TOT CSI_RS slots processed     |         693 |         693 |
12:18:08.341987 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341987 CON 553 0 [RU] | PUSCH slots sent               |         403 |         403 |
12:18:08.341988 CON 553 0 [RU] | PUSCH C-Plane RX               |        9672 |        9672 |
12:18:08.341989 CON 553 0 [RU] | PUSCH U-Plane TX               |           0 |           0 |
12:18:08.341989 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341989 CON 553 0 [RU] | PRACH slots sent               |         201 |         201 |
12:18:08.341990 CON 553 0 [RU] | PRACH C-Plane RX               |         804 |         804 |
12:18:08.341990 CON 553 0 [RU] | PRACH U-Plane TX               |        9648 |        9648 |
12:18:08.341990 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341991 CON 553 0 [RU] | PUCCH slots sent               |         403 |         403 |
12:18:08.341991 CON 553 0 [RU] | PUCCH C-Plane RX               |       29016 |       29016 |
12:18:08.341992 CON 553 0 [RU] | PUCCH U-Plane TX               |           0 |           0 |
12:18:08.341992 CON 553 0 [RU] | SRS slots sent                 |           0 |           0 |
12:18:08.341993 CON 553 0 [RU] | SRS C-Plane RX                 |           0 |           0 |
12:18:08.341993 CON 553 0 [RU] | SRS U-Plane TX                 |           0 |           0 |
12:18:08.341993 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341994 CON 553 0 [RU] | Max UL type1 sections per slot |          96 |          96 |
12:18:08.341994 CON 553 0 [RU] | Max UL type3 sections per slot |          16 |          16 |
12:18:08.341995 CON 553 0 [RU] | Max DL type1 sections per slot |         418 |         418 |
12:18:08.341995 CON 553 0 [RU] | Max AGGR sections per slot     |         418 |         418 |
12:18:08.341995 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.341997 CON 553 0 [RU] | ONTIME U-Plane Slot 0 %        |       0.00% |       0.00% |
12:18:08.341998 CON 553 0 [RU] | ONTIME U-Plane Slot 1 %        |       0.00% |       0.00% |
12:18:08.341999 CON 553 0 [RU] | ONTIME U-Plane Slot 2 %        |       0.00% |       0.00% |
12:18:08.341999 CON 553 0 [RU] | ONTIME U-Plane Slot 3 %        |       0.00% |       0.00% |
12:18:08.342000 CON 553 0 [RU] | ONTIME U-Plane Slot 4 %        |       0.00% |       0.00% |
12:18:08.342000 CON 553 0 [RU] | ONTIME U-Plane Slot 5 %        |       0.00% |       0.00% |
12:18:08.342001 CON 553 0 [RU] | ONTIME U-Plane Slot 6 %        |       0.00% |       0.00% |
12:18:08.342001 CON 553 0 [RU] | ONTIME U-Plane Slot 7 %        |       0.00% |       0.00% |
12:18:08.342002 CON 553 0 [RU] | ONTIME U-Plane Slot 8 %        |       0.00% |       0.00% |
12:18:08.342003 CON 553 0 [RU] | ONTIME U-Plane Slot 9 %        |       0.00% |       0.00% |
12:18:08.342003 CON 553 0 [RU] | ONTIME U-Plane Slot 10 %       |       0.00% |       0.00% |
12:18:08.342004 CON 553 0 [RU] | ONTIME U-Plane Slot 11 %       |       0.00% |       0.00% |
12:18:08.342004 CON 553 0 [RU] | ONTIME U-Plane Slot 12 %       |       0.00% |       0.00% |
12:18:08.342005 CON 553 0 [RU] | ONTIME U-Plane Slot 13 %       |       0.00% |       0.00% |
12:18:08.342005 CON 553 0 [RU] | ONTIME U-Plane Slot 14 %       |       0.00% |       0.00% |
12:18:08.342006 CON 553 0 [RU] | ONTIME U-Plane Slot 15 %       |       0.00% |       0.00% |
12:18:08.342006 CON 553 0 [RU] | ONTIME U-Plane Slot 16 %       |       0.00% |       0.00% |
12:18:08.342007 CON 553 0 [RU] | ONTIME U-Plane Slot 17 %       |       0.00% |       0.00% |
12:18:08.342008 CON 553 0 [RU] | ONTIME U-Plane Slot 18 %       |       0.00% |       0.00% |
12:18:08.342008 CON 553 0 [RU] | ONTIME U-Plane Slot 19 %       |       0.00% |       0.00% |
12:18:08.342009 CON 553 0 [RU] | ONTIME U-Plane Slot 20 %       |       0.00% |       0.00% |
12:18:08.342009 CON 553 0 [RU] | ONTIME U-Plane Slot 21 %       |       0.00% |       0.00% |
12:18:08.342010 CON 553 0 [RU] | ONTIME U-Plane Slot 22 %       |       0.00% |       0.00% |
12:18:08.342010 CON 553 0 [RU] | ONTIME U-Plane Slot 23 %       |       0.00% |       0.00% |
12:18:08.342011 CON 553 0 [RU] | ONTIME U-Plane Slot 24 %       |       0.00% |       0.00% |
12:18:08.342011 CON 553 0 [RU] | ONTIME U-Plane Slot 25 %       |       0.00% |       0.00% |
12:18:08.342012 CON 553 0 [RU] | ONTIME U-Plane Slot 26 %       |       0.00% |       0.00% |
12:18:08.342012 CON 553 0 [RU] | ONTIME U-Plane Slot 27 %       |       0.00% |       0.00% |
12:18:08.342013 CON 553 0 [RU] | ONTIME U-Plane Slot 28 %       |       0.00% |       0.00% |
12:18:08.342013 CON 553 0 [RU] | ONTIME U-Plane Slot 29 %       |       0.00% |       0.00% |
12:18:08.342014 CON 553 0 [RU] | ONTIME U-Plane Slot 30 %       |       0.00% |       0.00% |
12:18:08.342014 CON 553 0 [RU] | ONTIME U-Plane Slot 31 %       |       0.00% |       0.00% |
12:18:08.342015 CON 553 0 [RU] | ONTIME U-Plane Slot 32 %       |       0.00% |       0.00% |
12:18:08.342016 CON 553 0 [RU] | ONTIME U-Plane Slot 33 %       |       0.00% |       0.00% |
12:18:08.342016 CON 553 0 [RU] | ONTIME U-Plane Slot 34 %       |       0.00% |       0.00% |
12:18:08.342017 CON 553 0 [RU] | ONTIME U-Plane Slot 35 %       |       0.00% |       0.00% |
12:18:08.342017 CON 553 0 [RU] | ONTIME U-Plane Slot 36 %       |       0.00% |       0.00% |
12:18:08.342018 CON 553 0 [RU] | ONTIME U-Plane Slot 37 %       |       0.00% |       0.00% |
12:18:08.342018 CON 553 0 [RU] | ONTIME U-Plane Slot 38 %       |       0.00% |       0.00% |
12:18:08.342019 CON 553 0 [RU] | ONTIME U-Plane Slot 39 %       |       0.00% |       0.00% |
12:18:08.342019 CON 553 0 [RU] | ONTIME U-Plane Slot 40 %       |       0.00% |       0.00% |
12:18:08.342020 CON 553 0 [RU] | ONTIME U-Plane Slot 41 %       |       0.00% |       0.00% |
12:18:08.342020 CON 553 0 [RU] | ONTIME U-Plane Slot 42 %       |       0.00% |       0.00% |
12:18:08.342021 CON 553 0 [RU] | ONTIME U-Plane Slot 43 %       |       0.00% |       0.00% |
12:18:08.342021 CON 553 0 [RU] | ONTIME U-Plane Slot 44 %       |       0.00% |       0.00% |
12:18:08.342022 CON 553 0 [RU] | ONTIME U-Plane Slot 45 %       |       0.00% |       0.00% |
12:18:08.342022 CON 553 0 [RU] | ONTIME U-Plane Slot 46 %       |       0.00% |       0.00% |
12:18:08.342023 CON 553 0 [RU] | ONTIME U-Plane Slot 47 %       |       0.00% |       0.00% |
12:18:08.342023 CON 553 0 [RU] | ONTIME U-Plane Slot 48 %       |       0.00% |       0.00% |
12:18:08.342024 CON 553 0 [RU] | ONTIME U-Plane Slot 49 %       |       0.00% |       0.00% |
12:18:08.342025 CON 553 0 [RU] | ONTIME U-Plane Slot 50 %       |       0.00% |       0.00% |
12:18:08.342025 CON 553 0 [RU] | ONTIME U-Plane Slot 51 %       |       0.00% |       0.00% |
12:18:08.342026 CON 553 0 [RU] | ONTIME U-Plane Slot 52 %       |       0.00% |       0.00% |
12:18:08.342026 CON 553 0 [RU] | ONTIME U-Plane Slot 53 %       |       0.00% |       0.00% |
12:18:08.342027 CON 553 0 [RU] | ONTIME U-Plane Slot 54 %       |       0.00% |       0.00% |
12:18:08.342027 CON 553 0 [RU] | ONTIME U-Plane Slot 55 %       |       0.00% |       0.00% |
12:18:08.342028 CON 553 0 [RU] | ONTIME U-Plane Slot 56 %       |       0.00% |       0.00% |
12:18:08.342028 CON 553 0 [RU] | ONTIME U-Plane Slot 57 %       |       0.00% |       0.00% |
12:18:08.342029 CON 553 0 [RU] | ONTIME U-Plane Slot 58 %       |       0.00% |       0.00% |
12:18:08.342029 CON 553 0 [RU] | ONTIME U-Plane Slot 59 %       |       0.00% |       0.00% |
12:18:08.342030 CON 553 0 [RU] | ONTIME U-Plane Slot 60 %       |       0.00% |       0.00% |
12:18:08.342030 CON 553 0 [RU] | ONTIME U-Plane Slot 61 %       |       0.00% |       0.00% |
12:18:08.342031 CON 553 0 [RU] | ONTIME U-Plane Slot 62 %       |       0.00% |       0.00% |
12:18:08.342031 CON 553 0 [RU] | ONTIME U-Plane Slot 63 %       |       0.00% |       0.00% |
12:18:08.342032 CON 553 0 [RU] | ONTIME U-Plane Slot 64 %       |       0.00% |       0.00% |
12:18:08.342033 CON 553 0 [RU] | ONTIME U-Plane Slot 65 %       |       0.00% |       0.00% |
12:18:08.342033 CON 553 0 [RU] | ONTIME U-Plane Slot 66 %       |       0.00% |       0.00% |
12:18:08.342034 CON 553 0 [RU] | ONTIME U-Plane Slot 67 %       |       0.00% |       0.00% |
12:18:08.342034 CON 553 0 [RU] | ONTIME U-Plane Slot 68 %       |       0.00% |       0.00% |
12:18:08.342035 CON 553 0 [RU] | ONTIME U-Plane Slot 69 %       |       0.00% |       0.00% |
12:18:08.342035 CON 553 0 [RU] | ONTIME U-Plane Slot 70 %       |       0.00% |       0.00% |
12:18:08.342036 CON 553 0 [RU] | ONTIME U-Plane Slot 71 %       |       0.00% |       0.00% |
12:18:08.342036 CON 553 0 [RU] | ONTIME U-Plane Slot 72 %       |       0.00% |       0.00% |
12:18:08.342037 CON 553 0 [RU] | ONTIME U-Plane Slot 73 %       |       0.00% |       0.00% |
12:18:08.342037 CON 553 0 [RU] | ONTIME U-Plane Slot 74 %       |       0.00% |       0.00% |
12:18:08.342038 CON 553 0 [RU] | ONTIME U-Plane Slot 75 %       |       0.00% |       0.00% |
12:18:08.342038 CON 553 0 [RU] | ONTIME U-Plane Slot 76 %       |       0.00% |       0.00% |
12:18:08.342039 CON 553 0 [RU] | ONTIME U-Plane Slot 77 %       |       0.00% |       0.00% |
12:18:08.342039 CON 553 0 [RU] | ONTIME U-Plane Slot 78 %       |       0.00% |       0.00% |
12:18:08.342040 CON 553 0 [RU] | ONTIME U-Plane Slot 79 %       |       0.00% |       0.00% |
12:18:08.342040 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.342041 CON 553 0 [RU] | AVG ONTIME U Slot 0 %          |       0.00% |
12:18:08.342041 CON 553 0 [RU] | AVG ONTIME U Slot 1 %          |       0.00% |
12:18:08.342042 CON 553 0 [RU] | AVG ONTIME U Slot 2 %          |       0.00% |
12:18:08.342042 CON 553 0 [RU] | AVG ONTIME U Slot 3 %          |       0.00% |
12:18:08.342042 CON 553 0 [RU] | AVG ONTIME U Slot 4 %          |       0.00% |
12:18:08.342043 CON 553 0 [RU] | AVG ONTIME U Slot 5 %          |       0.00% |
12:18:08.342043 CON 553 0 [RU] | AVG ONTIME U Slot 6 %          |       0.00% |
12:18:08.342043 CON 553 0 [RU] | AVG ONTIME U Slot 7 %          |       0.00% |
12:18:08.342044 CON 553 0 [RU] | AVG ONTIME U Slot 8 %          |       0.00% |
12:18:08.342044 CON 553 0 [RU] | AVG ONTIME U Slot 9 %          |       0.00% |
12:18:08.342045 CON 553 0 [RU] | AVG ONTIME U Slot 10 %         |       0.00% |
12:18:08.342045 CON 553 0 [RU] | AVG ONTIME U Slot 11 %         |       0.00% |
12:18:08.342045 CON 553 0 [RU] | AVG ONTIME U Slot 12 %         |       0.00% |
12:18:08.342046 CON 553 0 [RU] | AVG ONTIME U Slot 13 %         |       0.00% |
12:18:08.342046 CON 553 0 [RU] | AVG ONTIME U Slot 14 %         |       0.00% |
12:18:08.342046 CON 553 0 [RU] | AVG ONTIME U Slot 15 %         |       0.00% |
12:18:08.342047 CON 553 0 [RU] | AVG ONTIME U Slot 16 %         |       0.00% |
12:18:08.342047 CON 553 0 [RU] | AVG ONTIME U Slot 17 %         |       0.00% |
12:18:08.342047 CON 553 0 [RU] | AVG ONTIME U Slot 18 %         |       0.00% |
12:18:08.342048 CON 553 0 [RU] | AVG ONTIME U Slot 19 %         |       0.00% |
12:18:08.342048 CON 553 0 [RU] | AVG ONTIME U Slot 20 %         |       0.00% |
12:18:08.342048 CON 553 0 [RU] | AVG ONTIME U Slot 21 %         |       0.00% |
12:18:08.342049 CON 553 0 [RU] | AVG ONTIME U Slot 22 %         |       0.00% |
12:18:08.342049 CON 553 0 [RU] | AVG ONTIME U Slot 23 %         |       0.00% |
12:18:08.342049 CON 553 0 [RU] | AVG ONTIME U Slot 24 %         |       0.00% |
12:18:08.342049 CON 553 0 [RU] | AVG ONTIME U Slot 25 %         |       0.00% |
12:18:08.342050 CON 553 0 [RU] | AVG ONTIME U Slot 26 %         |       0.00% |
12:18:08.342050 CON 553 0 [RU] | AVG ONTIME U Slot 27 %         |       0.00% |
12:18:08.342050 CON 553 0 [RU] | AVG ONTIME U Slot 28 %         |       0.00% |
12:18:08.342051 CON 553 0 [RU] | AVG ONTIME U Slot 29 %         |       0.00% |
12:18:08.342051 CON 553 0 [RU] | AVG ONTIME U Slot 30 %         |       0.00% |
12:18:08.342051 CON 553 0 [RU] | AVG ONTIME U Slot 31 %         |       0.00% |
12:18:08.342052 CON 553 0 [RU] | AVG ONTIME U Slot 32 %         |       0.00% |
12:18:08.342052 CON 553 0 [RU] | AVG ONTIME U Slot 33 %         |       0.00% |
12:18:08.342052 CON 553 0 [RU] | AVG ONTIME U Slot 34 %         |       0.00% |
12:18:08.342053 CON 553 0 [RU] | AVG ONTIME U Slot 35 %         |       0.00% |
12:18:08.342053 CON 553 0 [RU] | AVG ONTIME U Slot 36 %         |       0.00% |
12:18:08.342053 CON 553 0 [RU] | AVG ONTIME U Slot 37 %         |       0.00% |
12:18:08.342054 CON 553 0 [RU] | AVG ONTIME U Slot 38 %         |       0.00% |
12:18:08.342054 CON 553 0 [RU] | AVG ONTIME U Slot 39 %         |       0.00% |
12:18:08.342054 CON 553 0 [RU] | AVG ONTIME U Slot 40 %         |       0.00% |
12:18:08.342055 CON 553 0 [RU] | AVG ONTIME U Slot 41 %         |       0.00% |
12:18:08.342055 CON 553 0 [RU] | AVG ONTIME U Slot 42 %         |       0.00% |
12:18:08.342055 CON 553 0 [RU] | AVG ONTIME U Slot 43 %         |       0.00% |
12:18:08.342056 CON 553 0 [RU] | AVG ONTIME U Slot 44 %         |       0.00% |
12:18:08.342056 CON 553 0 [RU] | AVG ONTIME U Slot 45 %         |       0.00% |
12:18:08.342056 CON 553 0 [RU] | AVG ONTIME U Slot 46 %         |       0.00% |
12:18:08.342057 CON 553 0 [RU] | AVG ONTIME U Slot 47 %         |       0.00% |
12:18:08.342057 CON 553 0 [RU] | AVG ONTIME U Slot 48 %         |       0.00% |
12:18:08.342057 CON 553 0 [RU] | AVG ONTIME U Slot 49 %         |       0.00% |
12:18:08.342058 CON 553 0 [RU] | AVG ONTIME U Slot 50 %         |       0.00% |
12:18:08.342058 CON 553 0 [RU] | AVG ONTIME U Slot 51 %         |       0.00% |
12:18:08.342058 CON 553 0 [RU] | AVG ONTIME U Slot 52 %         |       0.00% |
12:18:08.342059 CON 553 0 [RU] | AVG ONTIME U Slot 53 %         |       0.00% |
12:18:08.342059 CON 553 0 [RU] | AVG ONTIME U Slot 54 %         |       0.00% |
12:18:08.342059 CON 553 0 [RU] | AVG ONTIME U Slot 55 %         |       0.00% |
12:18:08.342060 CON 553 0 [RU] | AVG ONTIME U Slot 56 %         |       0.00% |
12:18:08.342060 CON 553 0 [RU] | AVG ONTIME U Slot 57 %         |       0.00% |
12:18:08.342060 CON 553 0 [RU] | AVG ONTIME U Slot 58 %         |       0.00% |
12:18:08.342061 CON 553 0 [RU] | AVG ONTIME U Slot 59 %         |       0.00% |
12:18:08.342061 CON 553 0 [RU] | AVG ONTIME U Slot 60 %         |       0.00% |
12:18:08.342061 CON 553 0 [RU] | AVG ONTIME U Slot 61 %         |       0.00% |
12:18:08.342062 CON 553 0 [RU] | AVG ONTIME U Slot 62 %         |       0.00% |
12:18:08.342062 CON 553 0 [RU] | AVG ONTIME U Slot 63 %         |       0.00% |
12:18:08.342062 CON 553 0 [RU] | AVG ONTIME U Slot 64 %         |       0.00% |
12:18:08.342063 CON 553 0 [RU] | AVG ONTIME U Slot 65 %         |       0.00% |
12:18:08.342063 CON 553 0 [RU] | AVG ONTIME U Slot 66 %         |       0.00% |
12:18:08.342063 CON 553 0 [RU] | AVG ONTIME U Slot 67 %         |       0.00% |
12:18:08.342064 CON 553 0 [RU] | AVG ONTIME U Slot 68 %         |       0.00% |
12:18:08.342064 CON 553 0 [RU] | AVG ONTIME U Slot 69 %         |       0.00% |
12:18:08.342064 CON 553 0 [RU] | AVG ONTIME U Slot 70 %         |       0.00% |
12:18:08.342065 CON 553 0 [RU] | AVG ONTIME U Slot 71 %         |       0.00% |
12:18:08.342065 CON 553 0 [RU] | AVG ONTIME U Slot 72 %         |       0.00% |
12:18:08.342065 CON 553 0 [RU] | AVG ONTIME U Slot 73 %         |       0.00% |
12:18:08.342066 CON 553 0 [RU] | AVG ONTIME U Slot 74 %         |       0.00% |
12:18:08.342066 CON 553 0 [RU] | AVG ONTIME U Slot 75 %         |       0.00% |
12:18:08.342066 CON 553 0 [RU] | AVG ONTIME U Slot 76 %         |       0.00% |
12:18:08.342067 CON 553 0 [RU] | AVG ONTIME U Slot 77 %         |       0.00% |
12:18:08.342067 CON 553 0 [RU] | AVG ONTIME U Slot 78 %         |       0.00% |
12:18:08.342067 CON 553 0 [RU] | AVG ONTIME U Slot 79 %         |       0.00% |
12:18:08.342068 CON 553 0 [RU] |----------------------------------------------|
12:18:08.342068 CON 553 0 [RU] | WORST AVG ONTIME U Slot %      |       0.00% |
12:18:08.342068 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.342069 CON 553 0 [RU] | WORST ONTIME U-Plane Slot %    |       0.00% |       0.00% |
12:18:08.342076 CON 553 0 [RU] | WORST ONTIME DL C-Plane Slot % |       0.00% |       0.00% |
12:18:08.342077 CON 553 0 [RU] | WORST ONTIME UL C-Plane Slot % |       0.00% |       0.00% |
12:18:08.342077 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.342078 CON 553 0 [RU] | DL C EARLY PACKETS             |           0 |           0 |
12:18:08.342078 CON 553 0 [RU] | DL C ON TIME PACKETS           |       88004 |       88004 |
12:18:08.342079 CON 553 0 [RU] | DL C LATE PACKETS              |           0 |           0 |
12:18:08.342079 CON 553 0 [RU] | DL U EARLY PACKETS             |           0 |           0 |
12:18:08.342079 CON 553 0 [RU] | DL U ON TIME PACKETS           |      503748 |      503597 |
12:18:08.342080 CON 553 0 [RU] | DL U LATE PACKETS              |         767 |        1303 |
12:18:08.342080 CON 553 0 [RU] | UL C EARLY PACKETS             |           0 |           0 |
12:18:08.342081 CON 553 0 [RU] | UL C ON TIME PACKETS           |        4028 |        4028 |
12:18:08.342081 CON 553 0 [RU] | UL C LATE PACKETS              |           0 |           0 |
12:18:08.342082 CON 553 0 [RU] | DL C ON TIME PACKET %          |     100.00% |     100.00% |
12:18:08.342084 CON 553 0 [RU] | DL U ON TIME PACKET %          |      99.85% |      99.74% |
12:18:08.342085 CON 553 0 [RU] | UL C ON TIME PACKET %          |     100.00% |     100.00% |
12:18:08.342085 CON 553 0 [RU] | DL C EARLY SLOTS               |           0 |           0 |
12:18:08.342085 CON 553 0 [RU] | DL C ON TIME SLOTS             |           0 |           0 |
12:18:08.342086 CON 553 0 [RU] | DL C LATE SLOTS                |           0 |           0 |
12:18:08.342086 CON 553 0 [RU] | DL U EARLY SLOTS               |           0 |           0 |
12:18:08.342087 CON 553 0 [RU] | DL U ON TIME SLOTS             |           0 |           0 |
12:18:08.342087 CON 553 0 [RU] | DL U LATE SLOTS                |           0 |           0 |
12:18:08.342087 CON 553 0 [RU] | UL C EARLY SLOTS               |           0 |           0 |
12:18:08.342088 CON 553 0 [RU] | UL C ON TIME SLOTS             |           0 |           0 |
12:18:08.342088 CON 553 0 [RU] | UL C LATE SLOTS                |           0 |           0 |
12:18:08.342089 CON 553 0 [RU] | DL C ON TIME SLOTS %           |       0.00% |       0.00% |
12:18:08.342090 CON 553 0 [RU] | DL U ON TIME SLOTS %           |       0.00% |       0.00% |
12:18:08.342090 CON 553 0 [RU] | UL C ON TIME SLOTS %           |       0.00% |       0.00% |
12:18:08.342091 CON 553 0 [RU] | DL C NOT ON TIME SLOTS %       |       0.00% |       0.00% |
12:18:08.342092 CON 553 0 [RU] | DL U NOT ON TIME SLOTS %       |       0.00% |       0.00% |
12:18:08.342092 CON 553 0 [RU] | UL C NOT ON TIME SLOTS %       |       0.00% |       0.00% |
12:18:08.342093 CON 553 0 [RU] |------------------------------------------------------------|
12:18:08.342093 CON 553 0 [RU] | DL C AVG ON TIME SLOTS %       |       0.00% |
12:18:08.342094 CON 553 0 [RU] | DL C MIN ON TIME SLOTS %       |       0.00% |
12:18:08.342094 CON 553 0 [RU] | DL U AVG ON TIME SLOTS %       |       0.00% |
12:18:08.342095 CON 553 0 [RU] | DL U MIN ON TIME SLOTS %       |       0.00% |
12:18:08.342095 CON 553 0 [RU] | UL C AVG ON TIME SLOTS %       |       0.00% |
12:18:08.342096 CON 553 0 [RU] | UL C MIN ON TIME SLOTS %       |       0.00% |
12:18:08.342096 CON 553 0 [RU] | DL C AVG NOT ON TIME SLOTS %   |       0.00% |
12:18:08.342097 CON 553 0 [RU] | DL U AVG NOT ON TIME SLOTS %   |       0.00% |
12:18:08.342097 CON 553 0 [RU] | UL C AVG NOT ON TIME SLOTS %   |       0.00% |
12:18:08.342097 CON 553 0 [RU] |----------------------------------------------|
12:18:08.342097 CON 553 0 [RU]  ORAN Timing:
12:18:08.342098 CON 553 0 [RU]  dl_c_plane_timing_delay: 470
12:18:08.342098 CON 553 0 [RU]  dl_c_plane_window_size: 51
12:18:08.342098 CON 553 0 [RU]  ul_c_plane_timing_delay: 336
12:18:08.342098 CON 553 0 [RU]  ul_c_plane_window_size: 51
12:18:08.342098 CON 553 0 [RU]  dl_u_plane_timing_delay: 345
12:18:08.342098 CON 553 0 [RU]  dl_u_plane_window_size: 51
12:18:08.342098 CON 553 0 [RU]  ul_u_plane_tx_offset: 231
12:18:08.342098 CON 553 0 [RU]  ul_u_plane_tx_offset_srs: 231
12:18:08.342098 CON 553 0 [RU] Finalizing...
12:18:08.342098 CON 553 0 [RU] Done, Bye!
Exiting bg_fmtlog_collector - log queue ever was full: 0
malloc_consolidate(): unaligned fastbin chunk detected
Aborted

From the testmac logs, I can see that some uplink packets are received and continue for a few seconds as below.

12:17:59.140004 CON 512 0 [MAC.SCF] cell_init: cell_id=0 fapi_type=SCF global_tick=18446744073709551615 first_init=1
12:17:59.140021 CON 512 0 [MAC.SCF] cell_config: cell_id=0 target_cell_id=0 phyCellId=41
12:17:59.140051 CON 512 0 [MAC.SCF] cell_init: cell_id=1 fapi_type=SCF global_tick=18446744073709551615 first_init=1
12:17:59.140052 CON 512 0 [MAC.SCF] cell_config: cell_id=1 target_cell_id=1 phyCellId=42
12:17:59.140328 CON 512 0 [MAC.SCF] cell_config: cell_id=0 failed: error_code=2
12:17:59.154112 CON 512 0 [MAC.SCF] cell_config: cell_id=0 OK
12:17:59.154113 CON 512 0 [MAC.SCF] cell_start: cell_id=0 fapi_type=SCF global_tick=18446744073709551615
12:17:59.154287 CON 512 0 [MAC.SCF] cell_config: cell_id=1 failed: error_code=2
12:17:59.248337 CON 512 0 [MAC.SCF] cell_config: cell_id=1 OK
12:17:59.248337 CON 512 0 [MAC.SCF] cell_start: cell_id=1 fapi_type=SCF global_tick=18446744073709551615
12:18:06.520100 CON 513 0 [APP.CONFIG] Current TAI offset: 0s
12:18:07.520024 CON 513 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL   28.96 Mbps  318 Slots | Prmb  119 | HARQ 7632 | SR    0 | CSI1 1908 | CSI2 1908 | SRS    0 | ERR   82 | INV 4656 | Slots 2000
12:18:07.520025 CON 513 0 [MAC.FAPI] Cell  1 | DL 1544.14 Mbps 1600 Slots | UL   28.96 Mbps  318 Slots | Prmb  116 | HARQ 7632 | SR    0 | CSI1 1908 | CSI2 1908 | SRS    0 | ERR   82 | INV 4640 | Slots 2000
12:18:08.520020 CON 513 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  189.26 Mbps  398 Slots | Prmb  699 | HARQ 9552 | SR    0 | CSI1 2388 | CSI2 2388 | SRS    0 | ERR    2 | INV  228 | Slots 4000
12:18:08.520021 CON 513 0 [MAC.FAPI] Cell  1 | DL 1544.14 Mbps 1600 Slots | UL  189.26 Mbps  398 Slots | Prmb  697 | HARQ 9552 | SR    0 | CSI1 2388 | CSI2 2388 | SRS    0 | ERR    2 | INV  192 | Slots 4000
12:18:09.520022 CON 513 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 6000
12:18:09.520023 CON 513 0 [MAC.FAPI] Cell  1 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 6000
12:18:10.520021 CON 513 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL   22.61 Mbps  311 Slots | Prmb  521 | HARQ 7464 | SR    0 | CSI1 1866 | CSI2 1866 | SRS    0 | ERR   88 | INV 4770 | Slots 8000
12:18:10.520022 CON 513 0 [MAC.FAPI] Cell  1 | DL 1544.14 Mbps 1600 Slots | UL   22.61 Mbps  311 Slots | Prmb  521 | HARQ 7464 | SR    0 | CSI1 1866 | CSI2 1866 | SRS    0 | ERR   88 | INV 4770 | Slots 8000
12:18:11.520022 CON 513 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL    0.00 Mbps  300 Slots | Prmb  500 | HARQ 7200 | SR    0 | CSI1 1800 | CSI2 1800 | SRS    0 | ERR  100 | INV 5400 | Slots 10000
12:18:11.520023 CON 513 0 [MAC.FAPI] Cell  1 | DL 1544.14 Mbps 1600 Slots | UL    0.00 Mbps  300 Slots | Prmb  500 | HARQ 7200 | SR    0 | CSI1 1800 | CSI2 1800 | SRS    0 | ERR  100 | INV 5400 | Slots 10000

The ru-emulator is running on a server with an Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz (12 cores).

Has anyone faced a similar issue? Could this be related to CPU performance limitations?

Any suggestions or insights would be greatly appreciated.

2

Hi @benji_huang,

Can you please share your testmac, cuphycontroller and ru_emulator config files? Can you also try a single cell test?

Thank you.

3

Hi @bkecicioglu

Thanks you for your reply. Please find the attached configuration files below.
And I would like to correct my earlier post: the server has 16 cores, not 12.

config.txt (12.3 KB)
cuphycontroller_F08_CG1.txt (35.8 KB)
test_mac_config.txt (9.4 KB)

In the single-cell test, the results are as expected, so I believe the configuration is correct, except for the cell_group_num, which I modified according to the test case.

02:11:19.960018 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL    0.00 Mbps  300 Slots | Prmb    0 | HARQ 7200 | SR    0 | CSI1 1800 | CSI2 1800 | SRS    0 | ERR  100 | INV 5400 | Slots 24000
02:11:20.960018 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL   33.44 Mbps  320 Slots | Prmb  126 | HARQ 7680 | SR    0 | CSI1 1920 | CSI2 1920 | SRS    0 | ERR   80 | INV 4530 | Slots 26000
02:11:21.960017 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 28000
02:11:22.960017 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 30000
02:11:23.960018 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 32000
02:11:24.960017 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 34000
02:11:25.960019 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 36000
02:11:26.960015 CON 870 0 [MAC.FAPI] Cell  0 | DL 1544.14 Mbps 1600 Slots | UL  196.70 Mbps  400 Slots | Prmb  700 | HARQ 9600 | SR    0 | CSI1 2400 | CSI2 2400 | SRS    0 | ERR    0 | INV    0 | Slots 38000

Many thanks.

4

Hi @benji_huang ,

The ru-emulator is running on a server with an Intel(R) Xeon(R) Silver 4314 CPU @ 2.40GHz (16 cores).

Has anyone faced a similar issue? Could this be related to CPU performance limitations?

We have not verified ru emulator with this CPU. Given that you are able to run single cell scenario, this could be related to ru_emulator not keeping up.

Can you experiment with moving one of the cores to the UL as follows?

ru_emulator:

  ul_core_list: [2,3,4,5,6,7,8,9]
  dl_core_list: [10,11,12,13,14,15,16]

Can you also check/confirm stability of the PTP on your setup?

$sudo systemctl status ptp4l.service

Please also check here .

Thank you.

5

Hi @bkecicioglu

After applying the core configuration, the multi-cell test cases, including 3C and 4C, have all passed.

I’m wondering — is there a requirement that the UL core count must be at least 8 for multi-cell scenarios?

Many thanks.

6

Hi @benji_huang ,

The default core configurations are for the systems we verified. From the logs you shared, it seemed the UL was not keeping up. That is why I recommended to increase the number of UL cores.

The optimal core allocation depends the CPU performance. The max number of cells you can run will also be limited by the RU emulator performance.

Thank you.

7

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