Debug PHY_INTR0 phy:0 cil:0 st:0 vc:0 status

[khang.l4es]

Hi @ShaneCCC,

Could you help to instruct how to access the NVCSI registers (NVCSI_PHY_0_NVCSI_CIL_A_CONTROL_0, NVCSI_STREAM_0_INTR_STATUS_VC0_0) for the HW debugging purpose, please ?

This is quite urgent as we are being stuck/blocked during the integration of the FPGA bridging. To progress, we need to provide more info to the FPGA designer to do some tuning on the Tx side.

Some probably relevant discussion I found is :

Experiencing strange behavior on MIPI CSI2 stream without i2c

Thank you for the hint. The NVCSI_STREAM_0_INTR_STATUS_VC0_0 did not give me any info but in the TRM I found another register (NVCSI_STREAM_3_PF_CRC_0) that could give me the calculated and the received frame CRC. Reading Register NVCSI_STREAM_3_PF_CRC_0 cmd: devmem2 0x15a281d8 w result: /dev/mem opened. Memory mapped at address 0x7f8bca9000. Value at address 0x15A281D8 (0x7f8bca91d8): 0x631EA801 Which showed that the calculated and the received CRC did not match. calculated CRC: 0x631E r…

But I experienced the system hang/crash while trying to access the 0x15a281d8 address with devmem2.

And you said “This REG is in VI scope may need to disable the power gate to access it” in the following discussion Accessing VI_CFG_VGP1_0 register - #6 by ShaneCCC

Could you tell how to do this ?

Thanks in advance and best regards,
Khang