Disable USB3.0 and Reduce SSD speed

I have a custom carrier board. I need to disable USB3.0 speeds (just use USB 2) and set the max-lane-speed and num lanes for the M.2 SSD slot. This is just for power savings. I don’t need to repurpose the other lanes. I have device tree changes that work for Jetpack 5 but I’m struggling to get things working in Jetpack 6.

I have been attempting to follow the instructions at Jetson Orin NX and Nano Series — NVIDIA Jetson Linux Developer Guide 1 documentation and Kernel Customization — NVIDIA Jetson Linux Developer Guide 1 documentation and Bootloader — NVIDIA Jetson Linux Developer Guide 1 documentation .

Here is what I have so far:
I used the pinmux spreadsheet to create 3 dtsi files. I didn’t change any entries in the spreadsheet because I believe that the pinout is the same as the devkit board (and I didn’t need to change the pinout in Jetpack 5). I’m just trying to throttle some things. Let me know if that is an incorrect assumption.

I created two overlay files - one for USB and one for the SSD changes.

/ {
    compatible = "nvidia,tegra234";

    fragment@0 {
        target-path = "/bus@0/pcie@14160000";
        __overlay__ {
            /* Set to use 1 lane at pcie 1 speed */
            max-link-speed = <1>;
            num-lanes = <1>;
        };
    };  
};

and

/ {
    compatible = "nvidia,tegra234";

    fragment@0 {
        target-path = "/bus@0/padctl@3520000/usb3/lanes/usb3-0";
        __overlay__ {
            status = "disabled";
        };
    };

    fragment@1 {
        target-path = "/bus@0/padctl@3520000/ports/usb2-0";
        __overlay__ {
            /delete-property/ usb-role-switch;
        };
    };

    fragment@2 {
        target-path = "/bus@0/padctl@3520000/ports/usb3-0";
        __overlay__ {
            nvidia,usb2-companion = <0>;
            status = "disabled";
        };
    };

    fragment@3 {
        target-path = "/bus@0/i2c@c240000/fusb301@25";
        __overlay__ {
            status = "disabled";
        };
    };

};

These are the changes that are working fine in jetpack 5.

I created a top-level dts file that applies these overlays and updated values in board.conf for PINMUX_CONFIG, PMC_CONFIG, and DTB_FILE.

I think that I may need to update the BPFDTB_FILE as well. But I am unsure and it is unclear to me from the documentation what changes I would need to make to which files.

When I flash the device I can see in the logs that it is finding my custom dts/dtsi files. And I can look at the decompiled dtb output on the jetson itself. I can run dtc -I fs -O dts /sys/firmware/devicetree/base -o out.dts . When I look at out.dts, I can see my overlay fragments. However, lspci shows the SSD running at full speed with 4 lanes and lsusb -t shows that the USB ports are still functioning at USB3 speeds.

I would really appreciate any help to point me in the right direction.

There is directly a field for overlay in the board config. Please take a look.

I switched the DTB_FILE back to the regular jetson devkit one. I compiled my overlay files into .dtbo files. and added them to the OVERLAY_DTB_FILE variable. I attempted to reflash but it gets stuck in Step 3: Start the flashing process with Waiting for target to boot-up...

I have been working with chatgpt and gemini. They both say that what I want to do isn’t possible. The ODMDATA configurations determine the lanes and speeds for PCIE and USB and that those are loaded prior to the kernel.

Is this true? I want to make the PCIE changes for power savings but there is a flaw in the board where it can’t handle the USB3 speeds. If I can’t change this, then I would be stuck on jetpack 5.

I still don’t get what you want to do here.

Could you just share one brief comment for your purpose?

Your could ignore what chatgpt or gemini told you there because I don’t really think they are related…

I have a custom carrier board that works with Jetpack 5. I am trying to upgrade to Jetpack 6. I am struggling to figure out how to do that.

I don’t know if you are aware that … your comment basically provides a very non specific items to check.

I guess your main target here is the USB part so please read the document first.

If you stuck in “Waiting for target to boot-up…” during initrd flash, it means your USB device mode part in device tree was wrong.

Not sure if you really know what you are doing there.

For example, I don’t know why you are disabling role switch which makes OTG function not possible.

fragment@1 {
target-path = “/bus@0/padctl@3520000/ports/usb2-0”;
overlay {
/delete-property/ usb-role-switch;
};
};

I think that you are right that I’m not fully sure what I am doing. I have learned a lot though. I have shifted to using dtc to decomplile/compile changes to the device tree on the running device - which I can validate with a reboot.

I’m getting close. My changes to the SSD (pcie@14160000) are working as I intended. You are right that there were some mistakes for the USB. My board has a USB-C connector but I can’t run at USB3 speeds.

The usb2-0 fragment should be:

 fragment@1 {
        target-path = "/bus@0/padctl@3520000/ports/usb2-0";
        __overlay__ {
            mode = "host";
            /delete-property/ usb-role-switch;
        };
    };

Additionally in usb@3610000 I needed to remove usb3-0 from the phy-names and the phys variables.

I have been looking at dmesg and it looks like the USB related parts are coming up just fine with these changes.

I have a USB device that I can plug in. The device has an LED and should light up but it does not. When I look at cat /sys/kernel/debug/regulator/regulator_summary I see the following with the device plugged in:

   use open bypass  opmode voltage current     min     max

regulator-dummy                  1    0      0 unknown     0mV     0mA     0mV     0mV
VDD_1V8_HS                       1    1      0 unknown  1800mV     0mA  1800mV  1800mV
0-0050-vcc                    0                                 0mA     0mV     0mV
VDD_1V8_SYS                      1    0      0 unknown  1800mV     0mA  1800mV  1800mV
VDD_5V0_SYS                      6    5      0 unknown  5000mV     0mA  5000mV  5000mV
usb2-2-vbus                   1                                 0mA     0mV     0mV
usb2-0-vbus                   1                                 0mA     0mV     0mV
VDD_3V3_AO                    2    1      0 unknown 33000mV     0mA 33000mV 33000mV
3520000.padctl-avdd-usb    1                                 0mA     0mV     0mV
VDD_AV10_HUB                  2    1      0 unknown  1100mV     0mA  1100mV  1100mV
usb2-1-vbus                1                                 0mA     0mV     0mV
VDD_1V8_AO                    4    5      0 unknown  1800mV     0mA  1800mV  1800mV
14160000.pcie-vddio-pex-ctl   1                                 0mA     0mV     0mV
14100000.pcie-vddio-pex-ctl   0                                 0mA     0mV     0mV
140a0000.pcie-vddio-pex-ctl   1                                 0mA     0mV     0mV
141e0000.pcie-vddio-pex-ctl   0                                 0mA     0mV     0mV
3520000.padctl-vclamp-usb   1                                 0mA     0mV     0mV
VDD-3V3-SYS                      1    0      0 unknown  3300mV     0mA  3300mV  3300mV
VDD_3V3_SD                       0    0      0 unknown  3300mV     0mA  3300mV  3300mV
VDD_3V3_PCIE                     1    1      0 unknown  3300mV     0mA  3300mV  3300mV
140a0000.pcie-vpcie3v3        1                                 0mA     0mV     0mV

So I can see that the USB 2 buses are present but they don’t have any power. My present guess is that if I could figure out how to get power to the port, then I would be able to use my device.

Hi,

Want to clarify how things work here.

You need to provide your schematic. USB is more like a whole picture that we need to know the overall design there to tell what is missing.

Also, if you force your usb2-0 to host mode, then you won’t be able to flash it because you just disable OTG by yourself. I don’t know if you care about that or not, but that looks like a problem to me.

I looked into it and for jetpack 5 we flash the board using the nano devkit board and then we transfer the device to our carrier board and change the FDT parameter in the extlinux.conf file. I talked with our hardware people and we never got things to work with our controller chip with jetpack 5. It would be great if we could make that work. Here is some info from our schematic.

He said that they tried to use the fusb chip from the nano board, but that it was EOL and we weren’t able to acquire it so we switched it out for the ptn5150ahxmp. We presently disable the fusb301 section in the device tree, but maybe there is a way to modify it to make it work?