We have customized a carrier board and added USB 3.0 resources. The system is using Jetpack 6.2, but devices connected to this USB port are not recognized in the system. Do we need to modify the device tree file? If so, how should we modify it? The image below shows the resources we are using.
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Based on the provided context, it appears that you have a customized carrier board for the Jetson AGX Orin module, and you’ve added USB 3.0 resources to the board. However, devices connected to this USB port are not recognized by the system, which is running Jetpack 4.6.2.
To resolve this issue, you may need to modify the device tree file to configure the USB 3.0 resources correctly. The device tree file is a data structure that describes the hardware components of your system, including the USB ports.
Here’s a step-by-step guide to help you modify the device tree file:
- Identify the USB controller: In your case, the USB 3.0 resources are likely controlled by the xHCI (Extensible Host Controller Interface) controller. You’ll need to identify the xHCI controller node in the device tree file.
- Locate the device tree file: The device tree file for the Jetson AGX Orin module is typically located in the
kernel/dtsdirectory of the Linux kernel source tree. You can find the exact location by checking thearch/arm64/boot/dts/directory. - Modify the device tree file: Open the device tree file in a text editor and locate the xHCI controller node. You’ll need to add or modify the following properties:
usb3-phy: This property specifies the USB 3.0 PHY (Physical Layer) controller. You’ll need to set this property to the correct value for your USB 3.0 PHY controller.usb3-phy-names: This property specifies the names of the USB 3.0 PHY controllers. You’ll need to add the name of your USB 3.0 PHY controller to this list.xhci: This property specifies the xHCI controller. You’ll need to set this property to the correct value for your xHCI controller.
- Recompile the device tree file: After modifying the device tree file, you’ll need to recompile it using the
dtc(Device Tree Compiler) tool. - Update the kernel: Once you’ve recompiled the device tree file, you’ll need to update the kernel to use the new device tree file.
Here’s an example of how you might modify the device tree file:
&xhci {
usb3-phy = <&usb3_phy0>;
usb3-phy-names = "usb3-phy0";
xhci = <&xhci0>;
};
&usb3_phy0 {
compatible = "usb3-phy";
reg = <0x0 0x1000000>;
clocks = <&clk_usb3>;
clock-names = "usb3";
};
In this example, we’ve added the usb3-phy and usb3-phy-names properties to the xHCI controller node, and we’ve also defined a new node for the USB 3.0 PHY controller.
Comparison with other Jetson modules:
The device tree file modifications required for the Jetson AGX Orin module may differ from those required for other Jetson modules, such as the Jetson Xavier NX or Jetson Nano. This is because each module has its own unique hardware configuration, and the device tree file must be modified accordingly.
For example, the Jetson Xavier NX module uses a different USB controller, so the device tree file modifications would be different from those required for the Jetson AGX Orin module.
Conclusion:
Modifying the device tree file is a common requirement when working with customized carrier boards or adding new hardware components to a system. By following the steps outlined above, you should be able to modify the device tree file to configure the USB 3.0 resources correctly on your Jetson AGX Orin module.
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this is the decompiled dtb file. This is the source code of my device tree ,How can I modify it?
padctl@3520000 {
compatible = "nvidia,tegra234-xusb-padctl";
reg = <0x00 0x3520000 0x00 0x20000 0x00 0x3540000 0x00 0x10000>;
reg-names = "padctl\0ao";
interrupts = <0x00 0xa7 0x04>;
resets = <0x03 0x72>;
reset-names = "padctl";
status = "okay";
vclamp-usb-supply = <0xf5>;
avdd-usb-supply = <0xf6>;
phandle = <0xfa>;
pads {
usb2 {
clocks = <0x03 0xa5>;
clock-names = "trk";
lanes {
usb2-0 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfb>;
};
usb2-1 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfe>;
};
usb2-2 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xff>;
};
usb2-3 {
nvidia,function = "xusb";
status = "disabled";
#phy-cells = <0x00>;
};
};
};
usb3 {
lanes {
usb3-0 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0x100>;
};
usb3-1 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfc>;
};
usb3-2 {
nvidia,function = "xusb";
status = "disabled";
#phy-cells = <0x00>;
};
usb3-3 {
nvidia,function = "xusb";
status = "disabled";
#phy-cells = <0x00>;
};
};
};
};
ports {
usb2-0 {
status = "okay";
mode = "otg";
vbus-supply = <0xf7>;
usb-role-switch;
port {
endpoint {
remote-endpoint = <0xf8>;
phandle = <0x106>;
};
};
};
usb2-1 {
status = "okay";
mode = "host";
vbus-supply = <0xf9>;
};
usb2-2 {
status = "okay";
mode = "host";
vbus-supply = <0xf7>;
};
usb2-3 {
status = "disabled";
};
usb3-0 {
status = "okay";
nvidia,usb2-companion = <0x01>;
};
usb3-1 {
status = "okay";
nvidia,usb2-companion = <0x00>;
};
usb3-2 {
status = "disabled";
};
usb3-3 {
status = "disabled";
};
};
};
usb@3550000 {
compatible = "nvidia,tegra234-xudc";
reg = <0x00 0x3550000 0x00 0x8000 0x00 0x3558000 0x00 0x8000>;
reg-names = "base\0fpci";
interrupts = <0x00 0xa6 0x04>;
clocks = <0x03 0x109 0x03 0x10c 0x03 0x113 0x03 0x110>;
clock-names = "dev\0ss\0ss_src\0fs_src";
interconnects = <0x57 0x4c 0x58 0x57 0x4d 0x58>;
interconnect-names = "dma-mem\0write";
iommus = <0xf0 0x0f>;
power-domains = <0x03 0x0b 0x03 0x0a>;
power-domain-names = "dev\0ss";
nvidia,xusb-padctl = <0xfa>;
dma-coherent;
status = "okay";
phys = <0xfb 0xfc>;
phy-names = "usb2-0\0usb3-0";
};
usb@3610000 {
compatible = "nvidia,tegra234-xusb";
reg = <0x00 0x3610000 0x00 0x40000 0x00 0x3600000 0x00 0x10000 0x00 0x3650000 0x00 0x10000>;
reg-names = "hcd\0fpci\0bar2";
interrupts-extended = <0x01 0x00 0xa3 0x04 0x01 0x00 0xa4 0x04 0xfd 0x4c 0x04 0xfd 0x4d 0x04 0xfd 0x4e 0x04 0xfd 0x4f 0x04 0xfd 0x50 0x04 0xfd 0x51 0x04 0xfd 0x52 0x04>;
interrupt-names = "xhci\0mbox\0wake0\0wake1\0wake2\0wake3\0wake4\0wake5\0wake6";
clocks = <0x03 0x10b 0x03 0x10d 0x03 0x10c 0x03 0x113 0x03 0x0e 0x03 0x110 0x03 0x67 0x03 0x0e 0x03 0x64>;
clock-names = "xusb_host\0xusb_falcon_src\0xusb_ss\0xusb_ss_src\0xusb_hs_src\0xusb_fs_src\0pll_u_480m\0clk_m\0pll_e";
interconnects = <0x57 0x4a 0x58 0x57 0x4b 0x58>;
interconnect-names = "dma-mem\0write";
iommus = <0xf0 0x0e>;
power-domains = <0x03 0x0c 0x03 0x0a>;
power-domain-names = "xusb_host\0xusb_ss";
nvidia,xusb-padctl = <0xfa>;
dma-coherent;
status = "okay";
phys = <0xfb 0xfe 0xff 0x100 0xfc>;
phy-names = "usb2-0\0usb2-1\0usb2-2\0usb3-0\0usb3-1";
};
Could you please provide some guidance? The project is quite urgent
Document for the USB porting.
BTW, your schematic provides nothing helpful. Just one USBSS data line does not give any useful information.
这是线路连接到的位置，下面是我修改后的设备树padctl@3520000 {
compatible = “nvidia,tegra234-xusb-padctl”;
reg = <0x00 0x3520000 0x00 0x20000 0x00 0x3540000 0x00 0x10000>;
reg-names = “padctl\0ao”;
interrupts = <0x00 0xa7 0x04>;
resets = <0x03 0x72>;
reset-names = “padctl”;
status = “okay”;
vclamp-usb-supply = <0xf5>;
avdd-usb-supply = <0xf6>;
phandle = <0xfa>;
compatible = “nvidia,tegra234-xusb-padctl”;
reg = <0x00 0x3520000 0x00 0x20000 0x00 0x3540000 0x00 0x10000>;
reg-names = “padctl\0ao”;
interrupts = <0x00 0xa7 0x04>;
resets = <0x03 0x72>;
reset-names = “padctl”;
status = “okay”;
vclamp-usb-supply = <0xf5>;
avdd-usb-supply = <0xf6>;
phandle = <0xfa>;
pads {
usb2 {
clocks = <0x03 0xa5>;
clock-names = "trk";
lanes {
usb2-0 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfb>;
};
usb2-1 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfe>;
};
usb2-2 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xff>;
};
usb2-3 {
nvidia,function = "xusb";
status = "disabled";
#phy-cells = <0x00>;
};
};
};
usb3 {
lanes {
usb3-0 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0x100>;
};
usb3-1 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfc>;
};
usb3-2 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0x101>;
};
usb3-3 {
nvidia,function = "xusb";
status = "disabled";
#phy-cells = <0x00>;
};
};
};
};
ports {
usb2-0 {
status = "okay";
mode = "otg";
vbus-supply = <0xf7>;
usb-role-switch;
port {
endpoint {
remote-endpoint = <0xf8>;
phandle = <0x107>;
};
};
};
usb2-1 {
status = "okay";
mode = "host";
vbus-supply = <0xf9>;
};
usb2-2 {
status = "okay";
mode = "host";
vbus-supply = <0xf7>;
};
usb2-3 {
status = "disabled";
};
usb3-0 {
status = "okay";
nvidia,usb2-companion = <0x01>;
};
usb3-1 {
status = "okay";
nvidia,usb2-companion = <0x00>;
};
usb3-2 {
status = "okay";
nvidia,usb2-companion = <0x02>;
};
usb3-3 {
status = "disabled";
};
};
};
usb@3550000 {
compatible = "nvidia,tegra234-xudc";
reg = <0x00 0x3550000 0x00 0x8000 0x00 0x3558000 0x00 0x8000>;
reg-names = "base\0fpci";
interrupts = <0x00 0xa6 0x04>;
clocks = <0x03 0x109 0x03 0x10c 0x03 0x113 0x03 0x110>;
clock-names = "dev\0ss\0ss_src\0fs_src";
interconnects = <0x57 0x4c 0x58 0x57 0x4d 0x58>;
interconnect-names = "dma-mem\0write";
iommus = <0xf0 0x0f>;
power-domains = <0x03 0x0b 0x03 0x0a>;
power-domain-names = "dev\0ss";
nvidia,xusb-padctl = <0xfa>;
dma-coherent;
status = "okay";
phys = <0xfb 0xfc>;
phy-names = "usb2-0\0usb3-0";
nvidia,boost_cpu_freq = <0x4b0>;
};
usb@3610000 {
compatible = "nvidia,tegra234-xusb";
reg = <0x00 0x3610000 0x00 0x40000 0x00 0x3600000 0x00 0x10000 0x00 0x3650000 0x00 0x10000>;
reg-names = "hcd\0fpci\0bar2";
interrupts-extended = <0x01 0x00 0xa3 0x04 0x01 0x00 0xa4 0x04 0xfd 0x4c 0x04 0xfd 0x4d 0x04 0xfd 0x4e 0x04 0xfd 0x4f 0x04 0xfd 0x50 0x04 0xfd 0x51 0x04 0xfd 0x52 0x04>;
interrupt-names = "xhci\0mbox\0wake0\0wake1\0wake2\0wake3\0wake4\0wake5\0wake6";
clocks = <0x03 0x10b 0x03 0x10d 0x03 0x10c 0x03 0x113 0x03 0x0e 0x03 0x110 0x03 0x67 0x03 0x0e 0x03 0x64>;
clock-names = "xusb_host\0xusb_falcon_src\0xusb_ss\0xusb_ss_src\0xusb_hs_src\0xusb_fs_src\0pll_u_480m\0clk_m\0pll_e";
interconnects = <0x57 0x4a 0x58 0x57 0x4b 0x58>;
interconnect-names = "dma-mem\0write";
iommus = <0xf0 0x0e>;
power-domains = <0x03 0x0c 0x03 0x0a>;
power-domain-names = "xusb_host\0xusb_ss";
nvidia,xusb-padctl = <0xfa>;
dma-coherent;
status = "okay";
phys = <0xfb 0xfe 0xff 0x100 0xfc 0x101>;
phy-names = "usb2-0\0usb2-1\0usb2-2\0usb3-0\0usb3-1\0usb3-2";
};
fuse@3810000 {
compatible = "nvidia,tegra234-efuse";
reg = <0x00 0x3810000 0x00 0x10000>;
clocks = <0x03 0x28>;
clock-names = "fuse";
};
hardware-timestamp@3aa0000 {
compatible = "nvidia,tegra234-gte-lic";
reg = <0x00 0x3aa0000 0x00 0x10000>;
interrupts = <0x00 0x0b 0x04>;
nvidia,int-threshold = <0x01>;
#timestamp-cells = <0x01>;
status = "disabled";
phandle = <0x22f>;
};，但是接上模块后（5G模块）系统下还是识别不到这个USB3.0设备
Where is the USB2 signal on this port?
We have modified our onboard interface signals, integrating the USB 2.0 PORT and 3.0 port into a unified USB interface. The signal usage is as follows:
USB2.0 signal: USB2_D/USB2_M
USB3.0 signals: USBDP0_TXDP3(SS2_TXP)/DP0_TXDN3(SS2_TXN)/DP0_TXDP2(SS2_RXP)/DP0_TXDN2(SS2_RXN)
Currently, after plugging in a USB3.0 U-disk device, the system still only recognizes the USB2.0 protocol, and the USB3.0 protocol does not take effect.
And simultaneously modified the device tree content as follows:
padctl@3520000 {
compatible = "nvidia,tegra234-xusb-padctl";
reg = <0x00 0x3520000 0x00 0x20000 0x00 0x3540000 0x00 0x10000>;
reg-names = "padctl\0ao";
interrupts = <0x00 0xa7 0x04>;
resets = <0x03 0x72>;
reset-names = "padctl";
status = "okay";
vclamp-usb-supply = <0xf5>;
avdd-usb-supply = <0xf6>;
phandle = <0xfa>;
pads {
usb2 {
clocks = <0x03 0xa5>;
clock-names = "trk";
lanes {
usb2-0 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfb>;
};
usb2-1 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfe>;
};
usb2-2 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xff>;
};
usb2-3 {
nvidia,function = "xusb";
status = "disabled";
#phy-cells = <0x00>;
};
};
};
usb3 {
lanes {
usb3-0 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0x100>;
};
usb3-1 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0xfc>;
};
usb3-2 {
nvidia,function = "xusb";
status = "okay";
#phy-cells = <0x00>;
phandle = <0x101>;
};
usb3-3 {
nvidia,function = "xusb";
status = "disabled";
#phy-cells = <0x00>;
};
};
};
};
ports {
usb2-0 {
status = "okay";
mode = "otg";
vbus-supply = <0xf7>;
usb-role-switch;
port {
endpoint {
remote-endpoint = <0xf8>;
phandle = <0x107>;
};
};
};
usb2-1 {
status = "okay";
mode = "host";
vbus-supply = <0xf9>;
};
usb2-2 {
status = "okay";
mode = "host";
vbus-supply = <0xf7>;
};
usb2-3 {
status = "disabled";
};
usb3-0 {
status = "okay";
nvidia,usb2-companion = <0x01>;
};
usb3-1 {
status = "okay";
nvidia,usb2-companion = <0x00>;
};
usb3-2 {
status = "okay";
nvidia,usb2-companion = <0x02>;
};
usb3-3 {
status = "disabled";
};
};
};
usb@3550000 {
compatible = "nvidia,tegra234-xudc";
reg = <0x00 0x3550000 0x00 0x8000 0x00 0x3558000 0x00 0x8000>;
reg-names = "base\0fpci";
interrupts = <0x00 0xa6 0x04>;
clocks = <0x03 0x109 0x03 0x10c 0x03 0x113 0x03 0x110>;
clock-names = "dev\0ss\0ss_src\0fs_src";
interconnects = <0x57 0x4c 0x58 0x57 0x4d 0x58>;
interconnect-names = "dma-mem\0write";
iommus = <0xf0 0x0f>;
power-domains = <0x03 0x0b 0x03 0x0a>;
power-domain-names = "dev\0ss";
nvidia,xusb-padctl = <0xfa>;
dma-coherent;
status = "okay";
phys = <0xfb 0xfc>;
phy-names = "usb2-0\0usb3-0";
nvidia,boost_cpu_freq = <0x4b0>;
};
usb@3610000 {
compatible = "nvidia,tegra234-xusb";
reg = <0x00 0x3610000 0x00 0x40000 0x00 0x3600000 0x00 0x10000 0x00 0x3650000 0x00 0x10000>;
reg-names = "hcd\0fpci\0bar2";
interrupts-extended = <0x01 0x00 0xa3 0x04 0x01 0x00 0xa4 0x04 0xfd 0x4c 0x04 0xfd 0x4d 0x04 0xfd 0x4e 0x04 0xfd 0x4f 0x04 0xfd 0x50 0x04 0xfd 0x51 0x04 0xfd 0x52 0x04>;
interrupt-names = "xhci\0mbox\0wake0\0wake1\0wake2\0wake3\0wake4\0wake5\0wake6";
clocks = <0x03 0x10b 0x03 0x10d 0x03 0x10c 0x03 0x113 0x03 0x0e 0x03 0x110 0x03 0x67 0x03 0x0e 0x03 0x64>;
clock-names = "xusb_host\0xusb_falcon_src\0xusb_ss\0xusb_ss_src\0xusb_hs_src\0xusb_fs_src\0pll_u_480m\0clk_m\0pll_e";
interconnects = <0x57 0x4a 0x58 0x57 0x4b 0x58>;
interconnect-names = "dma-mem\0write";
iommus = <0xf0 0x0e>;
power-domains = <0x03 0x0c 0x03 0x0a>;
power-domain-names = "xusb_host\0xusb_ss";
nvidia,xusb-padctl = <0xfa>;
dma-coherent;
status = "okay";
phys = <0xfb 0xfe 0xff 0x100 0xfc 0x101>;
phy-names = "usb2-0\0usb2-1\0usb2-2\0usb3-0\0usb3-1\0usb3-2";
};
What is the vbus-supply control of this port?
Is it always-on or with a gpio?
Always powered, not applicable to GPIO mode
Latest update: Currently, after plugging in a USB flash drive with USB3.0 protocol, using dmesg -w will continuously display the following message in a loop:[ 246.140418] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 249.472768] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 252.803773] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 256.136487] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 259.468556] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 262.804642] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 266.140214] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 269.480890] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 272.813250] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 275.317507] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 277.689688] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 280.064059] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 283.402247] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 286.734931] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 290.066808] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 292.564936] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 295.899481] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 299.235318] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 302.567876] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 305.904303] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 309.236029] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 312.568426] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 315.904616] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 319.236264] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 322.573029] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 325.905205] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 329.241127] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 332.581346] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 335.079569] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 338.413983] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
[ 341.746130] tegra-xusb 3610000.usb: Firmware timestamp: 2023-02-10 03:48:10 UTC
I don’t think this is an issue related to software configuration. Please review the hardware design.
Thank you for your help. I would like to confirm that our previous solution only had one USB3.0 port and did not include a USB2.0 port, which resulted in the inability to recognize USB3.0 devices. By adding a USB2.0 port to the circuit, normal recognition was achieved. Is it necessary for a USB3.0 port on the Jetson platform to include a USB2.0 port?
Yes… a USB3 port needs to have a USB2 port with it to meet the standard.
Our device tree document also tells your that a USB3 must have a USB2 companion.
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