Does Conv2D support format, NCHW. Order size is not matching the number dimensions of TensorRT

Platform details:

linux18.04 LTS
GPU: GTX1070
nvidia driver:390.77
cuda: 9.0
cudnn: 9.0-v7.4
tensorflow: 1.12.0
tensorrt: 5.0


Dear everyone,

I am trying to transform my tensorflow model to tensorRT model.

The ‘conv2D’ is in my layers. And it is behind the ‘concat’ layer.

When I use the code as below to register my input.

parser->registerInput("Input", DimsNCHW(1, 3, 256, 256), UffInputOrder::kNCHW);

It returns some error.

ERROR: UFFParser: Parser error: g_net/enc1_1/Conv2D: Order size is not matching the number dimensions of TensorRT

So I modify the input.

parser->registerInput("Input", DimsCHW(3, 256, 256), UffInputOrder::kNCHW);

It returns some error.

ERROR: g_net/enc1_1/Conv2D: kernel weights has count 4800 but 102400 was expected

The correct weights size is 5 x 5 x 64 x 6 = 4800. And 102400 can be get by 5 x 5 x 64 x 64. And 64 is the width of the previous layer’s output tensor. I tested much and got the same result.

I also wrote a custom plugin to replace for the ‘concat’. When I modify the output format to HWC, it can be parsed successfully.

Thanks.

For TensorFlow, the uff parser automatically apply required format handling.
But, no matter the model is NCHW or NHWC, please remember to register your input blob with NCHW format.

refrence https://docs.nvidia.com/deeplearning/sdk/tensorrt-developer-guide/index.html#mnist_uff_keyconcepts

@lingchao.zhu were you able to solve this problem??

Hello,

  1. Order size is not matching the number dimensions of TensorR:
    I haven’t solved this. But you can try to convert the tensorflow model with specified batch size and then use the converted .uff file to parse the model with same batch size.
    https://qiita.com/dcm_sakai/items/0e13e2917adf55e92745 someone talks about this problem.

  2. Concat error

    I think it is mainly caused by the data format.
    Because the concat layer is using a constant as the parameter. For example, ‘1’ in NCHW format stands for ‘C’ but in NHWC format stands for ‘H’.

thanks for the detailed info.

if possible can u please help by glancing at this thread

https://devtalk.nvidia.com/default/topic/1061861/tensorrt/order-size-is-not-matching-the-number-dimensions-of-tensorrt/post/5377090/?offset=2#5377437

i have order size issue with a simple standalone code with batch size of 1.

Thanks once again.