Xilinx’s DMA Engine IP has a companion sample X86 linux driver implementation.
Xilinx asserts this sample code is not supported on ARM.
Eli the Xillybus Guy asserts (to paraphrase): X86 has coherent DMA and ARM platforms generally do not.
Coherent DMA is defined as an intrinsic mechanism that allows the CPU to know that memory address segments that in it’s cache working set have been invalidated because DMA has just changed the data in the currently cached memory segments.
What is the status of this behavior on Xavier? Please let me know.
If further questions need to be asked of me to better understand what i am talking about, dont hesitate to ask them!