Hi jonathanh,
We have a custom carrier board for the SOM, so we found I2S interface numbers from the pinmux excel. According to this, DMIC1_CLK, DMIC1_DAT, DMIC2_CLK and DMIC2_DAT pins (pins H5, G6, H6, G5) of the SOM are connected to I2S3 interface.
In the meantime we modified our system so that the Tegra is an I2S slave, all I2S clocks are generated by an external FPGA. So this is why the pinmux registers show the clocks as inputs.
Pinmux registers for all 4 I2S interfaces (with TRM chapter number and expected bit setting):
# I2S1 (8.31.7 -> [1:0]=0)
DIN: Bank: 0 Reg: 0x02431030 Val: 0x00000458 -> dap1_din_pj2
DOUT: Bank: 0 Reg: 0x02431038 Val: 0x00000400 -> dap1_dout_pj1
LRCK: Bank: 0 Reg: 0x02431028 Val: 0x00000454 -> dap1_fs_pj3
SCLK: Bank: 0 Reg: 0x02431040 Val: 0x00000454 -> dap1_sclk_pj0
# I2S3 (8.31.5 -> [1:0]=1)
DIN: Bank: 0 Reg: 0x02432008 Val: 0x00006451 -> dmic1_dat_pm0
DOUT: Bank: 0 Reg: 0x02432018 Val: 0x00006401 -> dmic2_clk_pm3
LRCK: Bank: 0 Reg: 0x02432000 Val: 0x00006455 -> dmic1_clk_pm1
SCLK: Bank: 0 Reg: 0x02432010 Val: 0x00006455 -> dmic2_dat_pm2
# I2S4 (8.31.5 -> [1:0]=0)
DIN: Bank: 0 Reg: 0x02432038 Val: 0x00006458 -> dap4_din_pcc2
DOUT: Bank: 0 Reg: 0x02432040 Val: 0x00006400 -> dap4_dout_pcc1
LRCK: Bank: 0 Reg: 0x02432030 Val: 0x00006454 -> dap4_fs_pcc3
SCLK: Bank: 0 Reg: 0x02432048 Val: 0x00006454 -> dap4_sclk_pcc0
#I2S2 (8.31.11 -> [1:0]=0)
DIN: Bank: 0 Reg: 0x02434000 Val: 0x00000458 -> dap2_din_pc3
DOUT: Bank: 0 Reg: 0x02434008 Val: 0x00000400 -> dap2_dout_pc2
LRCK: Bank: 0 Reg: 0x02434010 Val: 0x00000454 -> dap2_fs_pc4
SCLK: Bank: 0 Reg: 0x02434018 Val: 0x00000454 -> dap2_sclk_pc1
According to the Parker TRM they seem to be fine: bit[10] is 1 and bit[1:0] settings correspond with the register documentation (PULLUP on the DIN pins is my fault, but it should not matter).
amixer setting:
amixer -c 0 sset 'I2S1 Mux' 'ADMAIF1'
amixer -c 0 sset 'ADMAIF1 Mux' 'I2S1'
amixer -c 0 cset name='I2S1 codec bit format' 32
amixer -c 0 cset name='I2S1 input bit format' 32
amixer -c 0 sset 'I2S2 Mux' 'ADMAIF2'
amixer -c 0 sset 'ADMAIF2 Mux' 'I2S2'
amixer -c 0 cset name='I2S2 codec bit format' 32
amixer -c 0 cset name='I2S2 input bit format' 32
amixer -c 0 sset 'I2S3 Mux' 'ADMAIF3'
amixer -c 0 sset 'ADMAIF3 Mux' 'I2S3'
amixer -c 0 cset name='I2S3 codec bit format' 32
amixer -c 0 cset name='I2S3 input bit format' 32
amixer -c 0 sset 'I2S4 Mux' 'ADMAIF4'
amixer -c 0 sset 'ADMAIF4 Mux' 'I2S4'
amixer -c 0 cset name='I2S4 codec bit format' 32
amixer -c 0 cset name='I2S4 input bit format' 32
When I try to record something with
arecord -D hw:0,X -r 48000 -c 2 -f S32_LE rec.wav
(X is changed from 0 to 3), I get the correct data sent by the test I2S source for all channels except I2S3, where there is no data recorded at all (the wav file only contains the header).
When a play an 1 minute, 48kHz file with
aplay -D hw:0,X sawtooth.wav
it takes ~30 sec on the other channels (the sampling frequency generated by the FPGA is 96 kHz, so this is ok) and the serial I2S output of the Tegra changes correctly (verified with a logic analyzer). When I2S3 is used, playback takes ~2 sec and there is no change on the output.
I would guess that this is the maximum performance of ADMA, so the output of the DMA is not limited by any read handshake?
Regards,
Peter