Enabling UART7 on TX2 using Jetpack 4.2

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi,

I am trying to activate UART7 on a TX2 using Jetpack 4.2. I edited tegra186-soc-uart.dtsi and changed the status attribute from “disabled” to “okay”.

In addition, I edited tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb and set the port number to 255, in order to divert the BPMP console, as recommended in other forum threads.

In tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg the following entries are present:

pinmux.0x0c302040 = 0x00000400; # uart7_tx_pw6: uartg, tristate-disable, input-disable, lpdr-disable
pinmux.0x0c302038 = 0x00000458; # uart7_rx_pw7: uartg, pull-up, tristate-enable, input-enable, lpdr-disable

The device node /dev/ttyTHS6 shows up, and dmesg shows that the kernel detects the device correctly

[    3.909750] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 37, base_baud = 0) is a TEGRA_UART
[    3.915214] c280000.serial: ttyTHS2 at MMIO 0xc280000 (irq = 38, base_baud = 0) is a TEGRA_UART
[    3.923011] serial-tegra 3130000.serial: RX in PIO mode
[    3.924174] 3130000.serial: ttyTHS3 at MMIO 0x3130000 (irq = 39, base_baud = 0) is a TEGRA_UART
[    3.932947] c290000.serial: ttyTHS6 at MMIO 0xc290000 (irq = 40, base_baud = 0) is a TEGRA_UART

but a simple loopback test does not work. Is there anything else I’m missing?

Thanks.

3

hello tobik-arculus,

please also refer to similar discussion thread for reference, Topic 80992.
thanks

4

Thanks a lot for the cross-reference, @JerryChang. I double-checked the register values for uart7:

Bank: 1 Reg: 0x0c302038 Val: 0x00000458 -> uart7_rx_pw7
Bank: 1 Reg: 0x0c302040 Val: 0x00000400 -> uart7_tx_pw6

Bits [1:0] are 0 and according to the Parker SoC TRM

PM:
0 = UARTG
1 = RSVD1
2 = RSVD2
3 = RSVD3

that means uartg should be enabled. I believe this is configured correctly, but isn’t working as expected.

5

hello tobik-arculus,

  1. could you please disassembler the dtb file into txt file to review you’d configure port=255 to disable BPMP using UART7 correctly.
    for example, $ dtc -I dtb -O dts -o results.txt tegra.dtb

  2. could you please check kernel messages for suspect failures while accessing to uart7. $ dmesg
    thanks

6

  1. Checking BPMP diversion:

    #> ./kernel/dtc -I dtb -O dts -o results.dts ./bootloader/tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb

#> head -n10 results.dts 
/dts-v1/;

/ {
 #address-cells = <0x2>;
 #size-cells = <0x2>;
 
 serial {
     port = <0xff>;
     has_input;
 };

  2. As noted above, I see

    [    0.974743] c290000.serial: ttyTHS6 at MMIO 0xc290000 (irq = 40, base_baud = 0) is a TEGRA_UART

    in dmesg output. There is nothing indicating a problem with any of the active UARTS. Also while accessing /dev/ttyTHS6 with e.g. screen or minicom, there are no error messages from the kernel.

7

hello tobik-arculus,

once you customize the port as 0xff, may I also know how you update the dtb file?
for example,
you may use below commands to update tegra186-a02-bpmp-quill-p3310-1000-a00-00-te770d-ucm2.dtb
$ sudo ./flash.sh -k bpmp-fw-dtb jetson-tx2 mmcblk0p1

8

@JerryChang, thank you for asking. I did a full flash sequence via

./flash.sh -r jetson-tx2 mmcblk0p1

As far as I can see from the log, the tegra186-a02-bpmp-quill-p3310-1000-a00-00-te770d-ucm2.dtb is included in this process.

9

hello tobik-arculus,

since you already create ttyTHS6 serial.
please have communication use-case directly instead of having loopback test.
thanks