We are developing a custom logic on FPGA that supports both video input and output. Interfaced over PCIe on TX1 running R24.2, they are exported as V4L2 and FB devices in Linux.
The FPGA is capable of performing the DMA operation from/to FPGA DDR to/from TX1 DDR allocated via dma_alloc_coherant and v4l2 sub-system. Following errors are reported when DMA is enabled.
smmu_dump_pagetable(): fault_address=0x00000000fe000000 pa=0xffffffffffffffff bytes=ffffffffffffffff #pte=0 in L2
[ 40.569545] mc-err: (0) csr_afir: EMEM decode error on PDE or PTE entry
[ 40.576211] mc-err: status = 0x6000000e; addr = 0xfe000000
[ 40.581885] mc-err: secure: no, access-type: read, SMMU fault: nr-nw-s
Obviously we are getting this because there is no SMMU mapping for the PCIe to the allocated DDR location. What is the right way to achieve the necessary functionality?
- Should we allocate like above and create a mapping in SMMU? If so, what are the relevant APIs in TX1?
- Is it possible to create a IOVA mapping as and when memory is allocated? If so, what are the relevant APIs/flags in TX1?
Thanks in advance.