My driver code is using pci_alloc_consistent which probably uses dma_alloc_coherent underlying. I pass the dma handle via the BAR0 so that the FPGA knows the address to write to.

However, I am not getting any data from TX2.

I would like the MMU to be enabled so that it will not affect other processes.

Please help. Thanks in advance.

What is the version of the codebase you are using?
I hope you meant ‘SMMU’ by MMU in your update.
SMMU for PCIe is indeed enabled in all latest software releases.
To confirm if SMMU is enabled for PCIe or not, do the following

cd /sys/kernel/debug/12000000.iommu/masters/

if SMMU is enabled for PCIe, you should be able to see something like the following there.


Yes SMMU is enabled. I am using R28.

I am passing 0x0000000080000000 address to the FPGA, but I do not get any meaningful data

It is really difficult to provide any meaningful support with only this much info. Is FPGA PCIe endpoint properly configured at the hardware level (including its DMA engine etc…). What is the client device driver being used here and has it been verified on any other platform (like x86)?

Hi previously the driver and fpga works on x86 platform. The same fpga card is then plugged into the tx2 eval card. The fpga can also see the addresses I passed to it, however no data is transferred.

Will it help if I pass u the driver code or paste snippets of the code?

Yup… please share the driver. You can share it privately with me if you don’t want to make it public.

hi i am PM you. TYVM

Just to check if anyone knows how to solve this

Please give me some time and I’ll go through the driver and get back to you

Hi vidyas,

Any updates?

Please if anyone has encountered similar issues and resolved them, would deeply appreciate if you can point me to the correct direction!

Though not completely, I did go through your driver and it seems a bit complex and hence couldn’t really identify any issue straight away.
Can you please make sure that

  1. You are not using physical addresses to be accessed by DMA
  2. Not freeing any DMA address wrongly before it is accessed by DMA
    Please check the above points.