Pcie driver smmu error

I am developing a pci driver.
It tells the FPGA the address of the DMA memory and when the hardware generates an interrupt, the FPGA writes the data to the DMA memory.
However, when an interrupt appears, the following error occurs.

arm-smmu 12000000.iommu:Unhandled context fault: iova=0x00000000, fsynr=0xc0011, cb=21, sid17(0x11 - AFI), pgd =0, pud=0, pmd=0, pte=0
mc-err: vpr base=0:0, size=0, ctrl=1, override:(e01a8341, 1dc10c1, 2a800000, 2)
mc-err: (255) csw_afiw: MC request violates VPR requirements
mc-err: status = 0x00337031; addr = 0x3ffffffc0
mc-err: secure: yes, access-type: write
mc-err: unknown mcerr fault, int_status=0x00000000, ch_int_status=0x00000200,  hubc_int_status=0x00000000
mc-err: unknown mcerr fault, int_status=0x00000000, ch_int_status=0x00000200,  hubc_int_status=0x00000000
mc-err: unknown mcerr fault, int_status=0x00000000, ch_int_status=0x00000200,  hubc_int_status=0x00000000
mc-err: Too many MC errors; throttling prints

I saw https://forums.developer.nvidia.com/t/how-to-disable-smmu-in-jetpack-4-2/73927 and tried to disable smmu, but it still gives an error.
What should I do to fix this error?
I have jetpack 4.2.2 installed on the jetson tx2 board.
(An error occurs, but the data is normally written in the DMA memory)

I need more details about the issue.

  1. Are you doing DMA read or write?
    when the hardware generates an interrupt, the FPGA writes the data to the DMA memory.
  2. Interrupt is generated from FPGA to Tegra, right? Does FPGA driver in Tegra initiates DMA here?
  3. Can provide me link to datasheet which has DMA programming guidelines?
  4. Is is possible to share FPGA driver source code?

Few pointers which will help you in debug,

  1. arm smmu raised a fault with IOVA address 0x0 for write transaction.
  2. So, FPGA initiated a memory write transaction towards Tegra PCIe.
  3. There are two possibilities for this issue,
    a) FPGA DMA engine has wrong DST address(0x0) for a DMA write transaction. Check your DMA programming sequence.
    b) Linux PCIe driver in Tegra writes MSI address in FPGA’s MSI capability config register. FPGA initiates memory write to this address to raise PCIe MSI interrupt. If FPGA has bug and initiating memory write to 0x0 to raise MSI interrupt, then we can see arm smmu fault.

Check your SW for these two conditions.

Thanks,
Manikanta

Are you performing DMA reads or writes?
when the hardware generates an interrupt, the FPGA writes the data to the DMA memory.

-> Yes. I am writing to DMA.

FPGA to Tegra interrupt. Does Tegra’s FPGA driver start DMA here?

-> Yes. Here, the FPGA writes data to Tegra’s DMA.

Can you provide a link to a datasheet with DMA programming instructions?

-> What does a data sheet with DMA programming instructions mean?

Can you share the FPGA driver source code?

-> I sent my FPGA driver source code as a message.

Thank you

Hi,

FPGA vendor provides a datasheet, it’ll have programming guidelines for DMA, like where to program source/destination address, size and how to initiate DMA(ring doorbell).

Based on the error signature, I think you are not programming destination address in BAR registers. So, DMA engine is doing write to invalid address 0x0. I believe you have to use one of the dma addresses allocated using dma_alloc_coherent() in your driver.

Thanks,
Manikanta