Sorry for the late response.
HW design is quiet different from TX1 to TX2. We are looking into alternative approach to help you out.
Can you give more details on your usecase?
What usecase you are trying to generate using bit banging and what are the requirements?
The usecase for Gpio bit-banging is using to the gpio pins to serially program an FPGA. This is a startup type problem for our product. On the TX1, programming the FPGA using this method takes 6 seconds and is fast enough. On the TX2, programming the FPGA using the same method takes 140 seconds. ~20 times slower.
Requirements are to perform this bit-banging as fast as possible. On the TX1, this means bitbanging at ~ 10 MHz. On the TX2, we are currently limited to 0.5MHz. It would be good be able to also bitbang at a similar speed to TX1.
More details:
We are programming a Xilinx fpga using Slave serial mode. This involves toggling a clock line and a data line to load the configuration bitstream to the FPGA.
https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
thanks for the info.
While we are checking this.
Can you try below clock increase to get better result
root@tegra-ubuntu:/sys/kernel/debug/bpmp/debug/clk/axi_cbb# cat rate
115200000
root@tegra-ubuntu:/sys/kernel/debug/bpmp/debug/clk/axi_cbb# echo 409600000 > rate
or whatever is the max rate
root@tegra-ubuntu:/sys/kernel/debug/bpmp/debug/clk/axi_cbb# echo 1 > mrq_rate_locked
1 Like
Thanks for checking this,
Applying the clock increase has indeed improved performance.
Time to program FPGA before change (136 seconds).
Time to program FPGA after change ( 87 seconds).
echo 409600000 > /sys/kernel/debug/bpmp/debug/clk/axi_cbb/rate
echo 1 > /sys/kernel/debug/bpmp/debug/clk/axi_cbb/mrq_rate_locked
Are there any drawbacks of applying this change that we should be aware of?
Akmal
This increase the clock transfer rate for the backbone clock