GPIO Numbering on TX2

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

I just unboxed my TX2 Dev Kit earlier this week. Looking at a few forum threads and tutorials I see people exporting double digit pin numbers e.g. number 38 like here (https://devtalk.nvidia.com/default/topic/1025531/jetson-tx1/gpio-with-interrupts/#).

I make myself super user and then try to export pin 38 and I get back I/O error. I can however export pin number 219. Here’s the command:

# sudo sh -c "echo 38 > export"
sh: echo: I/O error

This is the page I have been looking at for pin info: http://www.jetsonhacks.com/nvidia-jetson-tx2-j21-header-pinout/. It seems to indicate the pin numbers run from 1 through 40. It does however have columns for “Sysfs GPIO”, but none of the numbers there are in my gpio file (see below).

How does the pin numbering work please?

Here’s my gpio file:

# cat /sys/kernel/debug/gpio
GPIOs 216-223, platform/max77620-gpio, max77620-gpio, can sleep:
 gpio-216 (                    |external-connection:) in  hi    
 gpio-221 (                    |spmic_gpio_input_5  ) in  lo    
 gpio-222 (                    |spmic_gpio_input_6  ) in  hi    

GPIOs 224-239, i2c/0-0077, tca9539, can sleep:
 gpio-227 (                    |en-vdd-sys          ) out lo    
 gpio-228 (                    |lcd-bias-en-rail    ) out hi    
 gpio-233 (                    |en-vdd-cam          ) out lo    
 gpio-234 (                    |en-vdd-cam-1v2      ) out lo    

GPIOs 240-255, i2c/0-0074, tca9539, can sleep:
 gpio-240 (                    |vdd-usb2-5v         ) out lo    
 gpio-241 (                    |en-vdd-ts-1v8       ) out hi    
 gpio-242 (                    |en-vdd-ts-hv-3v3    ) out hi    
 gpio-243 (                    |en-vdd-disp-3v3     ) out lo    
 gpio-244 (                    |vdd-fan             ) out hi    
 gpio-247 (                    |en-mdm-pwr-3v7      ) out lo    
 gpio-249 (                    |en-vdd-disp-1v8     ) out lo    
 gpio-250 (                    |dis-vdd-1v2         ) out hi    
 gpio-252 (                    |vdd-hdmi            ) out hi    
 gpio-253 (                    |en-vdd-cam-hv-2v8   ) out lo    

GPIOs 256-319, platform/c2f0000.gpio, tegra-gpio-aon:
 gpio-272 (                    |temp_alert          ) in  hi    
 gpio-312 (                    |Power               ) in  hi    
 gpio-313 (                    |Volume Up           ) in  hi    
 gpio-314 (                    |Volume Down         ) in  hi    
 gpio-315 (                    |wifi-wake-ap        ) in  lo    
 gpio-316 (                    |bt_host_wake        ) in  lo    

GPIOs 320-511, platform/2200000.gpio, tegra-gpio:
 gpio-381 (                    |reset_gpio          ) out lo    
 gpio-412 (                    |vdd-usb0-5v         ) out lo    
 gpio-413 (                    |vdd-usb1-5v         ) out lo    
 gpio-420 (                    |eqos_phy_reset      ) out hi    
 gpio-421 (                    |eqos_phy_intr       ) in  hi    
 gpio-424 (                    |wlan_pwr            ) out hi    
 gpio-426 (                    |cam1-pwdn           ) out lo    
 gpio-441 (                    |hdmi2.0_hpd         ) in  hi    
 gpio-444 (                    |wp                  ) in  hi    
 gpio-445 (                    |cd                  ) in  hi    
 gpio-446 (                    |en-vdd-sd           ) out lo    
 gpio-456 (                    |cam_pwdn_gpio       ) out lo    
 gpio-457 (                    |cam1-rst            ) out lo    
 gpio-461 (                    |cam_reset_gpio      ) out lo    
 gpio-479 (                    |external-connection:) in  hi    
 gpio-484 (                    |bt_ext_wake         ) out hi
2

One thing to notice about that file is that it doesn’t list unused GPIOs…it lists the assignment of GPIO which something has claimed use of. You can’t alter these without first removing whatever is using the GPIO.

For the dev carrier board J21 see this:
http://www.jetsonhacks.com/nvidia-jetson-tx2-j21-header-pinout/

You may want to read the last paragraph on J24 before testing, though this won’t affect everyone.

As an example note that gpio398 is pin 29 of J21. The gpio file you listed above does not show 398, so you know 398 can be used as GPIO. 398 is a number used in the kernel, 29 is a pin number on the dev carrier board J21 connector.

For all of the below I am using “sudo -s” to drop into a root shell, then you can use “exit” to leave the root shell.

If you place a volt meter on pin 29 (a convenient ground is pin 39) observe output after each of these:

# Demo of validating a pin is exported or not:
grep 398 /sys/kernel/debug/gpio
echo 398 > /sys/class/gpio/export
grep 398 /sys/kernel/debug/gpio
echo 398 > /sys/class/gpio/unexport
grep 398 /sys/kernel/debug/gpio
echo 398 > /sys/class/gpio/export

Note that there is a direction and level indicated in “/sys/kernel/debug/gpio”, and if you are to alter its output voltage after software inputs, then it needs to be “out”.

# Demo of in/out:
grep 398 /sys/kernel/debug/gpio
find /sys -name gpio398
# This shows "/sys/devices/2200000.gpio/gpio/gpio398"
cd /sys/devices/2200000.gpio/gpio/gpio398
cat direction
# shows "out" which matches /sys/kernel/debug/gpio
echo "in" > direction
grep 398 /sys/kernel/debug/gpio
# now shows "in"
echo "out" > direction
grep 398 /sys/kernel/debug/gpio
# now shows "out" again

Note that the path to this GPIO’s control has “2200000.gpio” in it. The “2200000” is the hexadecimal base address of the controller. This is listed in the Technical Reference Manual.

echo 1 > value; cat value
# voltage goes up
echo 0 > value; cat value
# voltage goes away

Unfortunately there seems to be a defect on my board (this was actually from the first batch of TX2 dev kits NVIDIA’s technical marketing received…it’s old). Despite J24 being set to 3.3V it never reaches 1.6V, and the operation itself of “1” or “0” is not reliable. If J24 is in the 3.3V position output should be 3.3V, but may not be…there seems to be an issue with the level shifter. Booting with J24 in the 3.3V position always has this issue (the 3.3V pin of J24 is valid at 3.3V). If you run into this issue (not everyone does), and if you use J24 in the 1.8V position, then this will be reliable. I recommend testing with J24 initially in the 1.8V position, and then validating if your board works with 3.3V I/O via J24.

Question for NVIDIA: What is the physical location of the U22 level shifter?

3

Thank you Linuxdev,

This helps me fill in some gaps. I browsed through the several hundred pages in chapter 8 of the Technical Reference Manual, but couldn’t find any table showing me how to go from “pin 29” to “gpio398” and back. Is there a simple formula to map between 29 and 398? Or do you know where I can find a table that lists all the pins?

4

The TRM is about the SoC and module, so it has no idea about which carrier pin is routed to which SoC or module pin. Different carrier boards imply different routing. Device trees can change this even on the same carrier board.

It’s easiest to just use that Jetson Hacks URL for pin numbering to GPIO numbering, but there are a lot of forum posts about this exact topic. This is one you might find useful (the TX2 is the t186, the TX1 is the t210):
[url]https://devtalk.nvidia.com/default/topic/1003613/jetson-tx2/gpio-doesn-t-work-/post/5125910/#5125910[/url]

5

Thank you - that forum helps.