ChenJian,
I was able to get more logs when the above happened again. From looks of it looks there is enough memory left. I have included tegrastats and perfkit results. The syslog shows the same results as last time. Let me know if I need to grab more logs to help us debug this.
Tegrastats
RAM 2630/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,20%,100%,19%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2630/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,11%,100%,12%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2630/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,12%,100%,17%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2630/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,24%,100%,22%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2630/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,15%,100%,13%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2630/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,20%,100%,13%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2631/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,28%,100%,23%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2630/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,26%,94%,18%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2631/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,100%,18%,17%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2631/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,100%,14%,18%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2631/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,18%,18%,96%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2631/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,19%,12%,100%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2631/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,18%,15%,100%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
RAM 2631/3854MB (lfb 1x1MB) SWAP 0/0MB (cached 0MB) cpu [100%,18%,16%,100%]@1734 EMC 0%@1600 AVP 0%@115 VDE 0 GR3D 0%@76 EDP limit 1734
Perfkit results:
gpu_idle,1,gpu,ratio,MAXWELL_GPU_SYS0,BOTH,GPU,Activity,UINT64,"Cycles the graphics engine and compute engine is idle."
l2_slice0_read_sectors_fb0,2,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector reads from the L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice0_read_sectors_atomic_fb0,3,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector reads for ATOM/RED to L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice0_read_sectors_tex_fb0,4,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector reads from TEX to L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice0_write_sectors_fb0,5,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector writes to the L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice0_write_sectors_atomic_fb0,6,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector writes for ATOM/RED to L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice0_write_sectors_tex_fb0,7,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector writes from TEX to L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice1_read_sectors_fb0,8,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector reads from the L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice1_read_sectors_atomic_fb0,9,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector reads for ATOM/RED to L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice1_read_sectors_tex_fb0,10,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector reads from TEX to L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice1_write_sectors_fb0,11,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector writes to the L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice1_write_sectors_atomic_fb0,12,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector writes for ATOM/RED to L2 cache in the given slice and FB partition. A sector is 32 bytes."
l2_slice1_write_sectors_tex_fb0,13,gpu,raw,MAXWELL_GPU_FBP0,COMPUTE,Cache,L2,UINT64,"Sector writes from TEX to L2 cache in the given slice and FB partition. A sector is 32 bytes."
sm_active_cycles_vsm0,15,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Activity,UINT64,"Number of cycles that this SM has at least one active warp. Increments by 0-1 per cycle per SM."
sm_active_cycles_vsm1,16,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Activity,UINT64,"Number of cycles that this SM has at least one active warp. Increments by 0-1 per cycle per SM."
sm_active_warps_vsm0,17,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Activity,UINT64,"Active warps per cycle on this SM. Increments by 0-64 per cycle per SM."
sm_active_warps_vsm1,18,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Activity,UINT64,"Active warps per cycle on this SM. Increments by 0-64 per cycle per SM."
sm_branches_diverged_vsm0,19,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Divergent branches by this VSM. This counter increments by one if at least one thread in a warp diverges (that is, follows a different execution path) via a data dependent conditional branch. Increments by 0-1 per cycle."
sm_branches_diverged_vsm1,20,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Divergent branches by this VSM. This counter increments by one if at least one thread in a warp diverges (that is, follows a different execution path) via a data dependent conditional branch. Increments by 0-1 per cycle."
sm_branches_executed_vsm0,21,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Branches taken by this VSM. This counter increments by one if at least one thread in a warp takes the branch. Increments by 0-1 per cycle."
sm_branches_executed_vsm1,22,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Branches taken by this VSM. This counter increments by one if at least one thread in a warp takes the branch. Increments by 0-1 per cycle."
sm_branches_taken_vsm0,23,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Increments by one if at least one thread in a warp takes the branch. Increments by 0-4 per cycle."
sm_branches_taken_vsm1,24,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Increments by one if at least one thread in a warp takes the branch. Increments by 0-4 per cycle."
sm_ctas_launched_vsm0,25,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Activity,UINT64,"Thread blocks launched. Increments by 1 per thread block launched."
sm_ctas_launched_vsm1,26,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Activity,UINT64,"Thread blocks launched. Increments by 1 per thread block launched."
sm_inst_executed_vsm0,27,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Instructions executed in this SM, not including replays. Increments by 0-8 per cycle per SM."
sm_inst_executed_vsm1,28,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Instructions executed in this SM, not including replays. Increments by 0-8 per cycle per SM."
sm_inst_executed_generic_loads_vsm0,29,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Generic load instructions executed by this SM."
sm_inst_executed_generic_loads_vsm1,30,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Generic load instructions executed by this SM."
sm_inst_executed_generic_stores_vsm0,31,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Generic store instructions executed by this SM."
sm_inst_executed_generic_stores_vsm1,32,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Generic store instructions executed by this SM."
sm_inst_executed_global_loads_vsm0,33,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Global load instructions executed by this SM."
sm_inst_executed_global_loads_vsm1,34,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Global load instructions executed by this SM."
sm_inst_executed_global_stores_vsm0,35,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Global store instructions executed by this SM."
sm_inst_executed_global_stores_vsm1,36,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Global,UINT64,"Global store instructions executed by this SM."
sm_inst_executed_local_loads_vsm0,37,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Local,UINT64,"Local load instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_local_loads_vsm1,38,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Local,UINT64,"Local load instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_local_stores_vsm0,39,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Local,UINT64,"Local store instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_local_stores_vsm1,40,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Local,UINT64,"Local store instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_shared_loads_vsm0,41,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Shared,UINT64,"Shared load instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_shared_loads_vsm1,42,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Shared,UINT64,"Shared load instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_shared_stores_vsm0,43,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Shared,UINT64,"Shared store instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_shared_stores_vsm1,44,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Shared,UINT64,"Shared store instructions executed by this SM. Increments by 0-1 per cycle per SM."
sm_inst_executed_surface_loads_vsm0,45,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Surface,UINT64,"Surface load instructions executed by this SM."
sm_inst_executed_surface_loads_vsm1,46,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Surface,UINT64,"Surface load instructions executed by this SM."
sm_inst_executed_surface_stores_vsm0,47,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Surface,UINT64,"Surface store instructions executed by this SM."
sm_inst_executed_surface_stores_vsm1,48,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,Memory,Surface,UINT64,"Surface store instructions executed by this SM."
sm_inst_issued_vsm0,49,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Instructions issued by the scheduler, including replays. Increments by 0-8 per cycle per SM."
sm_inst_issued_vsm1,50,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Instructions,UINT64,"Instructions issued by the scheduler, including replays. Increments by 0-8 per cycle per SM."
sm_pmevent_00_vsm0,51,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger00/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_00_vsm1,52,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger00/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_01_vsm0,53,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger01/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_01_vsm1,54,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger01/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_02_vsm0,55,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger02/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_02_vsm1,56,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger02/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_03_vsm0,57,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger03/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_03_vsm1,58,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger03/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_04_vsm0,59,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger04/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_04_vsm1,60,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger04/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_05_vsm0,61,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger05/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_05_vsm1,62,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger05/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_06_vsm0,63,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger06/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_06_vsm1,64,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger06/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_07_vsm0,65,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger07/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction executed."
sm_pmevent_07_vsm1,66,gpu,raw,MAXWELL_GPU_GPC0TPC0,COMPUTE,SM,Triggers,UINT64,"__prof_trigger07/pmevent instructions executed where at least 1 thread is not predicated off. Increments by 0-1 per warp instruction execut...