How To Enable SPI/SPIDev on 28.1 (On-Target)

hsdlcl · February 6, 2018, 2:37pm

Jetpack3.1 R28.1, after activite the SPI by following the steps on “Jetson/TX2 SPI - eLinux.org”, The GPIO will stop working.
but if I delete the “FDT /boot/dtb/tegra186-quill-p3310-1000-c03-00-base.dtb” in /boot/extlinux/extlinux.conf , GPIO works correctly, and the SPI fail.
My program need SPI and GPIO at same time, what should I do?

ShaneCCC · February 7, 2018, 3:00am

@hsdlcl
Copy your tegra186-quill-p3310-1000-c03-00-base.dtb.dtb to the …/Linux_for_Tegra/kernel/dtb/
then enter recovery mode to flash the DTB partition instead of modify the extlinux.conf to apply your dtb

sudo ./flash.sh -k kernel-dtb jetson-tx2 mmcblk0p1

hsdlcl · February 8, 2018, 2:37am

@ShaneCCC, Thank you very much, I did what you said, and the spidev3.0 shown correctly, but the GPIO still broken, when I export the GPIO398, its said “unable to open gpio398: No such file or directory”, and I re-flash the old dtb, the GPIO work fine, and the SPI failed again.

I will waiting for the on-host-machine-method provide by @david_evans_g. Thanks you again.

sebastian_w · February 8, 2018, 8:54am

I think your GPIO Number calculation is wrong. I had the same issue.

Please try this:

Get the GPIO Offset Value

dmesg | grep gpiochip_add_data

[    0.277513] gpiochip_add_data: registered GPIOs 448 to 511 on device: tegra-gpio-aon
[    0.325389] gpiochip_add_data: registered GPIOs 256 to 447 on device: tegra-gpio
[    0.358724] gpiochip_add_data: registered GPIOs 240 to 255 on device: tca9539
[    0.360692] gpiochip_add_data: registered GPIOs 224 to 239 on device: tca9539
[    0.379154] gpiochip_add_data: registered GPIOs 216 to 223 on device: max77620-gpio

Get the Port number

/* GPIOs implemented by main GPIO controller */
#define TEGRA_MAIN_GPIO_PORT_A 0
#define TEGRA_MAIN_GPIO_PORT_B 1
#define TEGRA_MAIN_GPIO_PORT_C 2
#define TEGRA_MAIN_GPIO_PORT_D 3
#define TEGRA_MAIN_GPIO_PORT_E 4
#define TEGRA_MAIN_GPIO_PORT_F 5
#define TEGRA_MAIN_GPIO_PORT_G 6
#define TEGRA_MAIN_GPIO_PORT_H 7
#define TEGRA_MAIN_GPIO_PORT_I 8
#define TEGRA_MAIN_GPIO_PORT_J 9
#define TEGRA_MAIN_GPIO_PORT_K 10
#define TEGRA_MAIN_GPIO_PORT_L 11
#define TEGRA_MAIN_GPIO_PORT_M 12
#define TEGRA_MAIN_GPIO_PORT_N 13
#define TEGRA_MAIN_GPIO_PORT_O 14
#define TEGRA_MAIN_GPIO_PORT_P 15
#define TEGRA_MAIN_GPIO_PORT_Q 16
#define TEGRA_MAIN_GPIO_PORT_R 17
#define TEGRA_MAIN_GPIO_PORT_T 18
#define TEGRA_MAIN_GPIO_PORT_X 19
#define TEGRA_MAIN_GPIO_PORT_Y 20
#define TEGRA_MAIN_GPIO_PORT_BB 21
#define TEGRA_MAIN_GPIO_PORT_CC 22
#define TEGRA_MAIN_GPIO_PORT_DD 23

#define TEGRA_MAIN_GPIO(port, offset) \
        ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)

/* GPIOs implemented by AON GPIO controller */
#define TEGRA_AON_GPIO_PORT_S 0
#define TEGRA_AON_GPIO_PORT_U 1
#define TEGRA_AON_GPIO_PORT_V 2
#define TEGRA_AON_GPIO_PORT_W 3
#define TEGRA_AON_GPIO_PORT_Z 4
#define TEGRA_AON_GPIO_PORT_AA 5
#define TEGRA_AON_GPIO_PORT_EE 6
#define TEGRA_AON_GPIO_PORT_FF 7

GPIO Number calculation

(GPIO_PORT_NUMBER * 8) + Offset (main GPIO oder AON GPIO) + Pinnumber.

Example: GPIO3_PAA.02
AA = 5
Offset = AON = 448
gpio = (5*8) + 448 +2 = 490

Set GPIO

echo "490" > /sys/class/gpio/export
echo "out" > /sys/class/gpio/gpio490/direction
echo "0" > /sys/class/gpio/gpio490/value
echo "1" > /sys/class/gpio/gpio490/value

hsdlcl · February 8, 2018, 1:59pm

@sebastian.weidmann ,You are right, after flash the new dtb file, the GPIO offset value changed

after flash the new dtb file, I got these info:
[ 0.271204] gpiochip_add_data: registered GPIOs 448 to 511 on device: tegra-gpio-aon
[ 0.316698] gpiochip_add_data: registered GPIOs 256 to 447 on device: tegra-gpio
[ 0.350599] gpiochip_add_data: registered GPIOs 240 to 255 on device: tca9539
[ 0.352499] gpiochip_add_data: registered GPIOs 224 to 239 on device: tca9539
[ 0.373340] gpiochip_add_data: registered GPIOs 216 to 223 on device: max77620-gpio

and before the flashing, the gpio offset value info is :
[ 0.271204] gpiochip_add_data: registered GPIOs 320 to 511 on device: tegra-gpio
[ 0.316698] gpiochip_add_data: registered GPIOs 256 to 319 on device: tegra-gpio-aon
[ 0.350599] gpiochip_add_data: registered GPIOs 240 to 255 on device: tca9539
[ 0.352499] gpiochip_add_data: registered GPIOs 224 to 239 on device: tca9539
[ 0.373340] gpiochip_add_data: registered GPIOs 216 to 223 on device: max77620-gpio

before flash the dtb file
I can contorl the GPIO398 gpio298 (298 389 398 481 388 list in the NVIDIA Jetson TX2 J21 Header Pinout - JetsonHacks)

hsdlcl · February 8, 2018, 2:06pm

@sebastian.weidmann @ShaneCCC I know the offset value is changed ,but I don’t know how to get the port number such as GPIO19_AUD_RST(the old GPIO398).

sorry, I am not good at the kernel things~~~

sebastian_w · February 8, 2018, 2:11pm

There is a Excel File in the Nvidia Download Area (Don´t know where exactly).
“Jetson-TX2-Generic-Customer-Pinmux-Template.xlsm”

GPIO19_AUD_RST = GPIO3_PJ.06

hsdlcl · February 8, 2018, 2:51pm

@sebastian.weidmann Thank you very much~~~~~~~

hsdlcl · February 8, 2018, 2:56pm

developer.nvidia.com/embedded/dlc/jetson-tx2-module-pinmux

asinglet · February 9, 2018, 2:47am

Thank you for making this guide!

After following it, I was able to get my TX2 to function as an SPI master. The difficulty for me has been getting this to function as a slave. I was reading some of the old threads on how this was done for the TX1, and I made the following changes:

In the kernel configuration, I added the lines

CONFIG_SPI_TEGRA114_SLAVE=y
CONFIG_SPI_TEGRA124_SLAVE=y

I added both, as I was unsure which to use.

Also, in the device tree, I some of the changes found in this thread https://devtalk.nvidia.com/default/topic/982253/tx1-in-spi-slave-mode-to-an-adc-/.

spi@3240000 {
		reg = <0x0 0x3240000 0x0 0x10000>;
		interrupts = <0x0 0x27 0x4>;
		dmas = <0x19 0x12 0x19 0x12>;
		clock-names = "spi", "pll_p", "clk_m";
		compatible = "nvidia,tegra124-spi-slave";
		reset-names = "spi";
		nvidia,dma-request-selector = <0x19 0x12>;
		clocks = <0xd 0x4a 0xd 0x10d 0xd 0x261>;
		resets = <0xd 0x2b>;
		status = "okay";
		dma-names = "rx", "tx";

		spi@0 {
			reg = <0x0>;
			compatible = "spidev";
			spi-max-frequency = <0x1312d00>;
		};
	};

However, the device does not seem to read the data from my SPI master. I notice that in the mentioned thread, there were no variables for the clocks or clock names, but when I got rid of these, dmesg | grep spi would return an error in getting the clock data.

If you have any advice on getting this to function as a slave, please let me know. I will continue experimenting in the mean time.

mgjet · February 23, 2018, 10:34am

Hi david_evans_g,

thanks for your guide. I got spidev but lost my Ethernet connectivity. ifconfig is just showing the lo device. Any ideas?

david_evans_g · February 23, 2018, 10:42am

Hi, ‘mgilge’.

There is a problem with this method, as highlighted earlier in this thread, unfortunately. The difficulty is, that applying this method (on-target) causes problems with the Ethernet because of modifications to the device tree and when you modify the device tree you’re missing parts related to ethernet. Prior to 28.1 it was much easier to enable SPI using the above method, but since 28.1 it just causes problems.The only feasible way of doing this (enabling SPI + keeping Ethernet happy) is to build it remotely on a host machine…

I’ve been meaning to provide a guide for on-target building (quite similar to the existing method in fact) but I’ve been so busy with my day-to-day job I haven’t found the time. I hope this helps you in the short term!

mgjet · February 23, 2018, 10:51am

Hi david_evans_g,
thanks for the quick answer. How would I get Ethernet back? Flash Jetpack again?
Is there a guide for host machine building with SPI support?

david_evans_g · February 23, 2018, 10:59am

Hi, ‘mgilge’

“How would I get Ethernet back? Flash Jetpack again?”
I believe so, unfortunately. Make sure to backup anything useful you have done beforehand (Sorry)…

“Is there a guide for host machine building with SPI support?”
Unfortunately not, but as I said earlier, the guide I’ve provided isn’t far off what is required.

It depends how much you need SPI for your project, I felt I learned a lot by getting used to building the kernel and associated SPI modules, tinkering with configurations, etc.

I’ve learned mostly all I know from ‘JetsonHacks’:
JetonHacks channel
[url]https://www.youtube.com/channel/UCQs0lwV6E4p7LQaGJ6fgy5Q[/url]

Build L4T on a host machine:
[url]JetPack 3.0 - NVIDIA Jetson TX2 - YouTube

mgjet · February 23, 2018, 11:04am

Thanks again!

To my understanding the guide under Jetson/TX2 SPI - eLinux.org is now safe to keep the Ethernet connectivity, thanks to the added step under “Decompiling Device Tree”:
$ sudo dtc -I fs -O dts -o extracted_proc.dts /proc/device-tree

Am I right?

david_evans_g · February 23, 2018, 11:14am

Hi, ‘mgilge’

If I recall correctly, that should be fine, I must admit I haven’t tried it myself, but I know someone else here on the forum made that change, I would recommend flashing a fresh L4T version first, then try that method.

I don’t understand the device tree well enough, but from what I recall my original solution only got part of the required device tree binary (from /boot/dtb), which was missing the ethernet parts (and probably other stuff too…) whereas the command you posted gives a copy of everything to work with (including ethernet). So you’re still using most of the original method in this post, but I would follow this [url]https://elinux.org/Jetson/TX2_SPI[/url]

mgjet · February 23, 2018, 1:09pm

Hi ‘david_evans_g’

I am down to the very last step where it says:

Enabling the New DTB
It’s better flash the DTB by flash command instead of modify the extlinux due plugin manager will broken may cause unknow problem like break the network interface. Below is the command flash the DTB only.

sudo ./flash.sh -r -k kernel-dtb jetson-tx2 mmcblk0p1

How would I flash thetson on target? Do you know where the “flash.sh” is located?

david_evans_g · February 23, 2018, 1:13pm

flash.sh is located in the JetPack folder you would have on your host build machine. It is a flash script for flashing several different items to the Jetson from a (host) build machine. Check your Jetpack folder that you use to flash the jetson from the very start.

guohoujin · February 26, 2018, 7:54am

Hi:

I can pass the Loopback Test on TX2 dev board by short J21 pin19/21 according to the following website.
But our carrier board use SPI0_MOSI/SPI0_MISO(F4/E4) as SPI interface, after add SPIDev in kernel and modify dtb files, I can’t pass the loopback test on our carrier board. I tried to modify dtb file to enable /dev/spi0.0, /dev/spi1.0, /dev/spi2.0, /dev/spi3.0, but it doesn’t work.

https://elinux.org/Jetson/TX1_SPI
https://elinux.org/Jetson/TX2_SPI

Besides, why TX2 dev board J21 pin19/21 is SPI3 interface? The two pins connect to SPI1 as pin name, even if in Jetson-TX2-Generic-Customer-Pinmux-Template.xlsm, the customer usage is SPI4.

asgomez · June 5, 2018, 7:47am

Hi, Sebastian.

I’ve found this on another post:

I think spi0, spi1 and spi3 are on the J21, J22 and J23 respectively.
spi0 = "/spi@3210000";
spi1 = "/spi@c260000";
spi2 = "/spi@3230000";
spi3 = "/spi@3240000";
spi4 = "/aon_spi@c260000";
qspi6 = "/spi@3270000";

SOM connector Kernel’s space Adrress Connector’s pins
SPI1 SPI3 “/spi@3240000”; J21 19, 21, 23, 24

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How To Enable SPI/SPIDev on 28.1 (On-Target)

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