SPI setup issues with Jetson Nano B01 DevKit

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
1

I’m using a stock Jetson Nano B01 DevKit with Jetpack 4.6.4 and am unable to get SPI working for either the SPI1 or SPI2 pins. Both fail the simple loopback test (spidev_test) referenced here: Jetson Nano trouble using SPI

sudo ./spidev_test -D /dev/spidev0.0 -g16 -zz
using device: /dev/spidev0.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 0
bits per word: 8 bytes per word: 1
max speed: 10000000 Hz (10000 KHz)
no. runs: 1
Using seed:0x650bbad9
loop count = 0
using sequential pattern …
transfer bytes [16]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
transfer: Return actual transfer length: 16
receive bytes [16]
0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
mismatch index 1
^^^ 00 00 00 00 00 00 00 00 00 00 00 /dev/spidev0.0: TEST FAILED !!! (status:-1)

I’ve read through all of the forum posts I could find on this topic, but haven’t found a solution that works for me yet.

I started with a fresh installation of Jetpack 4.6.4 via SDKManager, then used jetson-io to enable SPI1 and SPI2, followed by rebooting.

I’ve confirmed that extlinux.conf FDT references the correct dtb filename.
When this didn’t work, I tried manually editing the file (kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb) to replace the “rsvd*” references with “spi*” references and recompiling, as suggested in several posts. Still no luck.

Some relevant system state checks are below:
cat /etc/nv_tegra_release

R32 (release), REVISION: 7.4, GCID: 33514132, BOARD: t210ref, EABI: aarch64, DATE: Fri Jun 9 04:25:08 UTC 2023

dmesg | grep spi
[ 0.475131] iommu: Adding device 7000d400.spi to group 7
[ 0.475401] iommu: Adding device 7000d600.spi to group 8
[ 0.475678] iommu: Adding device 70410000.spi to group 9
[ 3.741574] tegra-qspi 70410000.spi: Prod settings list not found
[ 3.749795] qspi_mtd spi32766.0: MX25U3235F (4096 Kbytes)
[ 3.749803] qspi_mtd spi32766.0: mtd .name = spi32766.0, .size = 0x400000 (4MiB) .erasesize = 0x00001000 (4KiB) .numeraseregions = 0

dmesg | grep gpio
[ 0.588622] gpio gpiochip0: gpio-line-names specifies 240 line names but there are 256 lines on the chip
[ 0.589791] GPIO line 6 (system-suspend-gpio) hogged as output/high
[ 0.590318] gpiochip_setup_dev: registered GPIOs 0 to 255 on device: gpiochip0 (tegra-gpio)
[ 0.647464] gpiochip_setup_dev: registered GPIOs 504 to 511 on device: gpiochip1 (max77620-gpio)
[ 0.673179] extcon-gpio-states extcon:extcon@1: Cable state:0, cable id:0
[ 4.053338] i2c-mux-gpio cam_i2cmux: 2 port mux on Tegra I2C adapter adapter
[ 4.166693] FAN:gpio request success.
[ 5.326693] tegradc tegradc.1: No hpd-gpio in DT
[ 5.395946] input: gpio-keys as /devices/gpio-keys/input/input3

ls -lt /dev/gpio*
crw------- 1 root root 254, 1 Sep 20 14:08 /dev/gpiochip1
crw-rw---- 1 root gpio 254, 0 Sep 20 14:08 /dev/gpiochip0

ls -lt /dev/spi*
crw-rw---- 1 root gpio 153, 0 Sep 20 14:08 /dev/spidev0.0
crw-rw---- 1 root gpio 153, 1 Sep 20 14:08 /dev/spidev0.1
crw-rw---- 1 root gpio 153, 2 Sep 20 14:08 /dev/spidev1.0
crw-rw---- 1 root gpio 153, 3 Sep 20 14:08 /dev/spidev1.1

sudo cat /sys/kernel/debug/gpio | grep -i spi
gpio-12 (SPI1_MOSI )
gpio-13 (SPI1_MISO )
gpio-14 (SPI1_SCK )
gpio-15 (SPI1_CS0 )
gpio-16 (SPI0_MOSI )
gpio-17 (SPI0_MISO )
gpio-18 (SPI0_SCK )
gpio-19 (SPI0_CS0 )
gpio-20 (SPI0_CS1 )
gpio-232 (SPI1_CS1 )

sudo cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
A: 0:0 64 40 40 24 00 00 000000
B: 0:1 f0 00 00 00 00 00 000000
C: 0:2 1f 00 00 18 00 00 000000
D: 0:3 00 00 00 00 00 00 000000
E: 1:0 40 00 00 00 00 00 000000
F: 1:1 00 00 00 00 00 00 000000
G: 1:2 0c 00 00 00 00 00 000000
H: 1:3 fd 99 00 60 00 00 000000
I: 2:0 07 07 03 02 00 00 000000
J: 2:1 f0 00 00 00 00 00 000000
K: 2:2 00 00 00 00 00 00 000000
L: 2:3 00 00 00 00 00 00 000000
M: 3:0 00 00 00 00 00 00 000000
N: 3:1 00 00 00 00 00 00 000000
O: 3:2 00 00 00 00 00 00 000000
P: 3:3 00 00 00 00 00 00 000000
Q: 4:0 00 00 00 00 00 00 000000
R: 4:1 00 00 00 00 00 00 000000
S: 4:2 a0 80 00 00 00 00 000000
T: 4:3 01 01 00 00 00 00 000000
U: 5:0 00 00 00 00 00 00 000000
V: 5:1 01 00 00 00 00 00 000000
W: 5:2 00 00 00 00 00 00 000000
X: 5:3 78 08 08 70 00 60 606000
Y: 6:0 06 00 00 02 00 00 000000
Z: 6:1 0f 08 08 04 00 06 020600
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 01 00 00 00 00 00 000000
CC: 7:0 92 80 80 10 00 12 121200
DD: 7:1 01 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

From what I could infer from several other posts, it seems like the issue might be with the gpios hanging onto the pins (e.g. C: 0:2 1f 00 00 18 00 00 000000).

I tried removing the gpio-input = <… 0x10 0x11 0x12 0x13 0x14…> as suggested in this post: Jetson Nano SPI Bus Not Working - #10 by KevinFFF, but SPI still doesn’t work and it had no impact on the sudo cat /sys/kernel/debug/tegra_gpio output.

I’m new to working with device trees and it’s unclear to me what to look for to find the root cause of this. Any guidance on next steps would be appreciated.

3

Hi iflybri2,

Are you using Jetson Nano devkit with eMMC or SD module?

Have you referred to that thread step-by-step w/o any issue?

Could you share the current pinmux configuration on your board?

$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
4

Hi Kevin,

Thanks for the quick response. I’m currently using the B01 DevKit with SD module.

Regarding the referenced post, I was unable to find the .dtsi file that you reference in “method 1” on my system, so I have only attempted “method 2”.

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006044 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006044 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006044 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006048 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006048 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002040 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002000 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002040 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002040 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002040 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002040 -> qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp
5

I’m also attaching the flash log in case it is useful. In looking at it just now I do see that it reports an error, though it’s not clear whether this is relevant to the SPI issue or not. Please let me know if this gives any insight.
NV_L4T_FLASH_NANO_WITH_OS_IMAGE_COMP.log (23.2 KB)

6

For the method 1, you would need to sync the kernel source and build kernel and dtb image.

It seems your pinmux for SPI pins are configured correctly.

Actually, you could just modify the dtb under /boot/dtb/ w/o flashing the board to verify.

Are you using the Jetson Nano devkit with SD module?

8

Hi bmedower,

Are you working with @iflybri2? Or just your another account?

There should be many dtb under /boot. The exact dtb you are using should be /boot/dtb/kernel_XXX.dtb, or you could check the flash log.

It would take me some time to check this on my local setup.

May I know what’s your current status for verifying SPI loopback test on the devkit?
Could you send the SPI packet?

9

Hi Kevn,

I attached my entire flash log a few replies back. The flash log references this file:

copying dtbfile(/home/iflybri/nvidia/nvidia_sdk/JetPack_4.6.4_Linux_JETSON_NANO_TARGETS/Linux_for_Tegra/kernel/dtb/tegra210-p3448-0000-p3449-0000-b00.dtb)... done.

This file was modified on the Jetson Nano using jetsion-io.py to enable both SPI1 and SPI2. This created a new file called kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb that was placed in the /boot directory.

I then modified this file by hand as I noted in my original post on this thread. I have placed copies of this modified file in both /boot and /boot/dtb and renamed the flashed files in both directories to kernel_tegra210-p3448-0000-p3449-0000-b00.backup

My /boot/extlinux/extlinux.conf points to the /boot/…-user-custom.dtb file. I’ve pasted the contents below for reference:

TIMEOUT 30
DEFAULT JetsonIO

MENU TITLE L4T boot options

LABEL primary
      MENU LABEL primary kernel
      LINUX /boot/Image
      INITRD /boot/initrd
      APPEND ${cbootargs} quiet root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 nv-auto-config 

# When testing a custom kernel, it is recommended that you create a backup of
# the original kernel and add a new entry to this file so that the device can
# fallback to the original kernel. To do this:
#
# 1, Make a backup of the original kernel
#      sudo cp /boot/Image /boot/Image.backup
#
# 2, Copy your custom kernel into /boot/Image
#
# 3, Uncomment below menu setting lines for the original kernel
#
# 4, Reboot

# LABEL backup
#    MENU LABEL backup kernel
#    LINUX /boot/Image.backup
#    INITRD /boot/initrd
#    APPEND ${cbootargs}

LABEL JetsonIO
	MENU LABEL Custom Header Config: <HDR40 User Custom [2023-09-19-153504]>
	LINUX /boot/Image
	FDT /boot/kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb
	INITRD /boot/initrd
#	APPEND ${cbootargs} quiet root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 nv-auto-config
	APPEND ${cbootargs} root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 nv-auto-config

SPI loopback results still fail. These are the results with physical MISO/MOSI pins 19 and 21 on the header shorted to one another. I get the same failure if I try the SPI2 pins instead.

sudo ./spidev_test -D /dev/spidev0.0 -g16 -zz

using device: /dev/spidev0.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 0
bits per word: 8 bytes per word: 1
max speed: 10000000 Hz (10000 KHz)
no. runs: 1
Using seed:0x650da390
loop count = 0 
using sequential pattern ....
transfer bytes [16]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 
transfer: Return actual transfer length: 16
receive bytes [16]
0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
mismatch index 1 
^^^ 00 00 00 00 00 00 00 00 00 00 00 /dev/spidev0.0: TEST FAILED !!!!! (status:-1)
10

You don’t need to do these.
After using Jetson-IO to generate the kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb, it would load this dtb at boot up. (as you could see, it has also added the entry for this dtb in extlinux.conf)
You could just refer to Method 2 to decompile it → remove GPIO input for SPI pins → assemble it back to dtb.

11

Hi Kevin,

I tried using jetson-io first, before modifying anything by hand and that had the same results - spidev_test fails. I would not have bothered modifying things by hand if the -user-custom.dtb file that jetson-io created worked. Can you please give more detailed instructions to clarify what you mean by “remove GPIO input for SPI pins”. I thought that’s what I was doing by making the manual edits to the .dts file and then recompiling to .dtb but the edits I made didn’t have the desired effect.

12

This is Step2 in Jetson Nano SPI Bus Not Working - Jetson & Embedded Systems / Jetson Nano - NVIDIA Developer Forums.

You could also share your current kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb from your board for me to check.

13

You’re referring to this section, correct? I mentioned in my first post to this thread that I’ve already done this and it doesn’t solve the issue. Can you please share a known-good dtb file for a Jetson Nano B01 DevKit (SD card version) that has the SPI ports working?

14

I’m attaching 3 dts files here.

This is the decompiled dtb that installed with Jetpack4.6.4:
kernel_tegra210-p3448-0000-p3449-0000-b00.txt (I’m not sure why, but when I upload this file to the forum it is being renamed ‘temp.txt’)

This is the decompiled dtb that was created by jetson-io.py: kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.txt

This is the decompiled dtb after my manual edit, following the process in forum post you referred to: kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom-EditedStep2.txt

Please let me know if additional edits need to be made. If you can share a known-good file with me, I’d really appreciate it.
temp.txt (318.9 KB)
kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.txt (320.7 KB)
kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom-EditedStep2.txt (320.7 KB)

15

Your modification for gpio-input is correct.

I’ve found the following node may cause the issue.
Please replace the following rsvd2 with spi2.

			spi2_mosi_pb4 {
				nvidia,pins = "spi2_mosi_pb4";
				nvidia,function = "rsvd2";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi2_miso_pb5 {
				nvidia,pins = "spi2_miso_pb5";
				nvidia,function = "rsvd2";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi2_sck_pb6 {
				nvidia,pins = "spi2_sck_pb6";
				nvidia,function = "rsvd2";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi2_cs0_pb7 {
				nvidia,pins = "spi2_cs0_pb7";
				nvidia,function = "rsvd2";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi2_cs1_pdd0 {
				nvidia,pins = "spi2_cs1_pdd0";
				nvidia,function = "rsvd1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

Please replace the following rsvd1 with spi1.

			spi1_mosi_pc0 {
				nvidia,pins = "spi1_mosi_pc0";
				nvidia,function = "rsvd1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_miso_pc1 {
				nvidia,pins = "spi1_miso_pc1";
				nvidia,function = "rsvd1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_sck_pc2 {
				nvidia,pins = "spi1_sck_pc2";
				nvidia,function = "rsvd1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_cs0_pc3 {
				nvidia,pins = "spi1_cs0_pc3";
				nvidia,function = "rsvd1";
				nvidia,pull = <0x2>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_cs1_pc4 {
				nvidia,pins = "spi1_cs1_pc4";
				nvidia,function = "rsvd1";
				nvidia,pull = <0x2>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};
16

Modified file with rsvd->spi changes made is attached. I’ve compiled this, copied it to /boot and modified the extlinux.conf file to point to it. Still failing spidev_test.

Can you please share a known-good .dtb file with me?

sudo ./spidev_test -D /dev/spidev0.0 -g16 -zz
using device: /dev/spidev0.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 0
bits per word: 8 bytes per word: 1
max speed: 10000000 Hz (10000 KHz)
no. runs: 1
Using seed:0x65124e83
loop count = 0 
using sequential pattern ....
transfer bytes [16]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 
transfer: Return actual transfer length: 16
receive bytes [16]
0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
mismatch index 1 
^^^ 00 00 00 00 00 00 00 00 00 00 00 /dev/spidev0.0: TEST FAILED !!!!! (status:-1)

kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom-EditedStep2_rsvd.txt (320.7 KB)

17

Actually, you don’t need to modify extlinux.conf because Jetson-IO has configured it correctly.

How do you get spidev_test?

Please let me check with my local setup for the working dtb.

18

How do you get spidev_test ?

From a link in another Nvidia developer forum post, but I don’t recall which one. I believe the moderator’s name was Shane. I doubt the issue is related to spidev_test, but if there’s something you’d like me to look at along these lines please suggest it.

The problem really seems like the pins are still behaving as GPIO instead of SPI. What else can influence this aside from the dtb file?

19

Please just run the following commands on your board to get spidev_test which has been verified from my side.

$ wget https://raw.githubusercontent.com/torvalds/linux/v4.9/tools/spi/spidev_test.c
$ gcc -o spidev_test spidev_test.c

Are you using the Jetson Nano with eMMC or SD module?

20

Kevin,

Are you using the Jetson Nano with eMMC or SD module?

This is the third time that I’ve told you that I’m using the SD module.

We’ve been working this problem for a week now and have made zero progress. It’s particularly frustrating that you don’t appear to be actually reading what I’m posting before you respond. I understand that you likely have many users to support but I’m really not understanding how it can be so difficult to enable a standard feature on a stock development kit that has been around for many years. Why is a known-good file not available to share? Can we please work together real time for a while when you get to the office to see if we can get this closed? I’m running out of time for a critical milestone I need to hit.

With regards to the spidev_test that you sent, this version appears to have different options than the one I was using and they don’t map one to one. What options should I be using for the loopback test for pins 19 & 21?

Usage: ./spidev_test [-DsbdlHOLC3]
  -D --device   device to use (default /dev/spidev1.1)
  -s --speed    max speed (Hz)
  -d --delay    delay (usec)
  -b --bpw      bits per word
  -i --input    input data from a file (e.g. "test.bin")
  -o --output   output data to a file (e.g. "results.bin")
  -l --loop     loopback
  -H --cpha     clock phase
  -O --cpol     clock polarity
  -L --lsb      least significant bit first
  -C --cs-high  chip select active high
  -3 --3wire    SI/SO signals shared
  -v --verbose  Verbose (show tx buffer)
  -p            Send data (e.g. "1234\xde\xad")
  -N --no-cs    no chip select
  -R --ready    slave pulls low to pause
  -2 --dual     dual transfer
  -4 --quad     quad transfer

I was guessing I should run it with the --loop option for a loopback test but when I try this, it says invalid argument:

sudo ./spidev_test -D /dev/spidev0.0 --loop
can't set spi mode: Invalid argument
Aborted

If I just run it with the --verbose flag I get this:

sudo ./spidev_test -D /dev/spidev0.0 --verbose
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D  | ......@....�..................�.
RX | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  | ................................

This looks like a failure to me, as Tx and Rx don’t match.

21

Sorry that I get confused with several SPI related topics.
Do you short PIN19 and PIN21 on 40-pins header?

The steps in the following link have been verified on the Jetson Nano devkit with SD module as yours.
Jetson Nano SPI Bus Not Working - #10 by KevinFFF

nvidia@nvidia-desktop:~$ sudo modprobe spidev
nvidia@nvidia-desktop:~$ sudo ./spidev_test -D /dev/spidev0.0 -v -p "HelloWorld123456789abcdef"
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | 48 65 6C 6C 6F 57 6F 72 6C 64 31 32 33 34 35 36 37 38 39 61 62 63 64 65 66 __ __ __ __ __ __ __  | HelloWorld123456789abcdef
RX | 48 65 6C 6C 6F 57 6F 72 6C 64 31 32 33 34 35 36 37 38 39 61 62 63 64 65 66 __ __ __ __ __ __ __  | HelloWorld123456789abcdef

Please try the following dtb under /boot from my setup.
kernel_tegra210-p3448-0000-p3449-0000-b00-user-custom.dtb (233.0 KB)

If it still could not work, I would suggest using SDKM to re-flash the board with JP4.6.4(R32.7.4) and follow that instructions in that link step-by-step.

22

Please try the following dtb under /boot from my setup.

Thank you for the file. Unfortunately spidev_test still fails:

sudo ./spidev_test -D /dev/spidev0.0 -v -p "HelloWorld123456789abcdef"
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | 48 65 6C 6C 6F 57 6F 72 6C 64 31 32 33 34 35 36 37 38 39 61 62 63 64 65 66 __ __ __ __ __ __ __  | HelloWorld123456789abcdef
RX | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 __ __ __ __ __ __ __  | .........................

Do you short PIN19 and PIN21 on 40-pins header?

Yes - They are shorted.

If it still could not work, I would suggest using SDKM to re-flash the board with JP4.6.4(R32.7.4) and follow that instructions in that link step-by-step.

I’ve been through this process using the steps in the link you shared with a fresh flash of JP4.6.4 installed via the SDKManager at least 5 times over the past few weeks. Unless there is something different to try I really don’t see the point. I have only attempted using “method 2” from that post. Can you please give step by step instructions for how to use the “method 1” that you reference there? I am unable to find any files on either my Jetson Nano or on my host machine that are of type “.dtsi” and the directory structure you reference doesn’t seem to exist either. Either they don’t exist or I’m looking in the wrong place.