Spi bus enable issue in b01 nano jetson

babbelal.patel1 · December 21, 2021, 10:55am

Hi Support Team,

I am doing enable spi bus through dtsi file but it’s not done. please check my all test scenarios.

Scenario1 : SPI Test using device tree with Micro SD card device: Please see my attached scenario1.png for details.

1.Install Jetpack 4.6 in Micro SD card device.
2.enable spi bus drive using blow command.
       cd /lib/modules/4.9.253-tegra/kernel/drivers/spi/
       sudo insmod spidev.ko
3.spi interface will be generated after execute above commands
       ls /dev/spidev
       spidev0.0  spidev0.1  spidev1.0  spidev1.1  
4.Load dtb file on running board.
5.Now Download below link and Test SPI bus after short Miso & mosi pins no 19 and 21 for spi1 .
       https://github.com/rm-hull/spidev-test
       cd spidev-test-master
       gcc spidev_test.c -o spidev_test
      ./spidev_test -D /dev/spidev0.0 -v -p "Hello@@"
      **NO output return**

Scenario2 SPI Test using jetson-io.py with Micro SD card device: Please see my attached scenario2.png for details.

1.Install Jetpack 4.6 in Micro SD card device.
2.enable spi bus drive using blow command.
     cd /lib/modules/4.9.253-tegra/kernel/drivers/spi/
     sudo insmod spidev.ko
3.spi interface will be generated after execute above commands
     ls /dev/spidev
     spidev0.0  spidev0.1  spidev1.0  spidev1.1
4. run jetson-io.py to enable spi1 and sp2 using bellow commands.
     sudo /opt/nvidia/jetson-io/jetson-io.py
5.Now Download below link and Test SPI bus after short Miso & mosi pins no 19 and 21 for spi1 .
https://github.com/rm-hull/spidev-test
     cd spidev-test-master
     gcc spidev_test.c -o spidev_test
    ./spidev_test -D /dev/spidev0.0 -v -p "Hello@@"
    **Output return here: Hello@@**

Scenario3: SPI Test using device tree with EMMC device: Please see my attached scenario3.png for details.

1.Install Jetpack 4.6 in EMMC device.
2.enable spi bus drive using blow command.
       cd /lib/modules/4.9.253-tegra/kernel/drivers/spi/
       sudo insmod spidev.ko
3.spi interface will be generated after execute above commands
       ls /dev/spidev
       spidev0.0  spidev0.1  spidev1.0  spidev1.1  
4.Load dtb file on running board.
5.Now Download below link and Test SPI bus after short Miso & mosi pins no 19 and 21 for spi1 .
       https://github.com/rm-hull/spidev-test
       cd spidev-test-master
       gcc spidev_test.c -o spidev_test
      ./spidev_test -D /dev/spidev0.0 -v -p "Hello@@"
      **NO output return**

Scenario4: SPI Test using jetson-io.py with EMMC device. Pease see scenario4.png for details

      **NO Option here to update spi pins in gui**

Test scenario1:

Test scenario2:

Test scenario3:

Test scenario4:

Thanks & regards,
Babbelal patel

tsteinle · January 7, 2022, 9:17pm

Hi,

I think you did not exit jetson-io.py with “Save and reboot to reconfigure pins”.
The pin configuration will be stored in a DT overlay and will be available only after reboot.

BTW your Test scenario2 seems to work as expected. RX equals TX. What is missing?

-Thomas

ShaneCCC · February 17, 2022, 10:44am

Please update the latest release for EMMC version Nano to run the jetson-io.py for SPI pin configure.

ankithsingh · February 19, 2022, 5:37am

hi @ShaneCCC .
We have tried working on it by doing the required changes in the p3448-0002*.dtb to enable the spi for the emmc module, we have loaded the following dtb file in the boot folder and rebooted it. Yet after rebooting the module we the spi pins haven’t been enabled. Can you please help with this.

Thank you

ankithsingh · February 22, 2022, 5:13am

Hi @ShaneCCC Could you please help in this

Thank you

ShaneCCC · February 22, 2022, 8:01am

Confirm the pin configure by below command.

sudo cat /sys/kernel/debug/tegra_gpio
sudo cat /sys/kernel/debug/tegra_pinctrl_reg |grep ‘spi’

ankithsingh · February 26, 2022, 7:45am

Hi @ShaneCCC I have tried the below GitHub link as directed in the dev forums link
GitHub - rt-net/JetsonNano_DT_SPI: SPI1 enabled DTS and flash-tools for Jetson Nano . I had no luck with this
and as referred by you
Enabling spidev on the jetson nano is hanging when flashing - #59 by ShaneCCC
can you please let me know where should I add the above patch ?
I am attaching the following dtb p3448-0002*.dtb for emmc module which I have tried still facing difficulty in loopback testing. Could you please help for this

Thank you so much, Will be waiting for your reply

tegra210-p3448-0002-p3449-0000-b00.dtb (231.7 KB)

ShaneCCC · March 9, 2022, 6:30am

Checking the which dtb was applied by below command first. Then update the dts to enable the pin for spi then apply correct dtb.

dmesg | grep -i kernel

Also confirm the pin configure by below command.

sudo cat /sys/kernel/debug/tegra_gpio
sudo cat /sys/kernel/debug/tegra_pinctrl_reg |grep ‘spi’

ankithsingh · March 16, 2022, 12:47pm

The b00.dtb file has been used, which has been flashed on the emmc module, after performing loopback testing we cannot receive the output.

We have shorted the SPI Pins as well 19 & 21

Thank you

ShaneCCC · March 16, 2022, 12:51pm

Short 19&21 is necessary for loopback test.

ankithsingh · March 16, 2022, 12:51pm

we have done that as well we have shorted the 19 & 21 pins for loopback testing

ShaneCCC · March 16, 2022, 12:53pm

OK, so does that mean you have no problem for this topic anymore?

ankithsingh · March 16, 2022, 12:59pm

After shorting and performing loopback testing we didn’t receive the desired output Please find the attachment

ShaneCCC · March 16, 2022, 1:43pm

Please check the pin configure by below command.

sudo cat /sys/kernel/debug/tegra_gpio
sudo cat /sys/kernel/debug/tegra_pinctrl_reg |grep ‘spi’

ankithsingh · March 16, 2022, 1:51pm

ShaneCCC · March 16, 2022, 2:00pm

The pin configure is incorrect. Below is correct value. It could be your device problem.

nvidia@nvidia-desktop:~$ sudo cat /sys/kernel/debug/tegra_gpio
[sudo] password for nvidia:
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 04 00 00 000000
 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 00 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 00 00 00 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 00 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 03 00 00 00 000000
 J: 2:1 00 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 80 80 00 00 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 02 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 70 00 60 606000
 Y: 6:0 02 00 00 02 00 00 000000
 Z: 6:1 0e 08 00 04 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 92 80 80 02 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000
nvidia@nvidia-desktop:~$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg |grep 'spi'
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006044 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006044 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006044 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006044 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006044 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 -> qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp

ankithsingh · March 16, 2022, 2:07pm

Could you please let me know what necessary changes to be made so I will try it accordingly

ShaneCCC · March 16, 2022, 2:36pm

Modify those pins spi1_xxx_xxx to “spi1” in device tree like below.

				nvidia,pins = "spi1_cs1_pc4";
				nvidia,function = "spi1";

ankithsingh · March 16, 2022, 3:03pm

The following changes has to be done in the dtsi file right?

ShaneCCC · March 16, 2022, 3:05pm

Yes, it could be done in the dts/dtsi files.

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