How to enable SPI communication on A203 carrier board and Jetson Nano Production Module

Please tell me how to enable the pins for SPI communication on the SeeedStudio A203 Carrier Board Version 2 with the Jetson Nano Module.

My hardware configuration looks like below.

  • Jetson Nano Production module (eMMC 16GB)
  • Seeed studio A203 (Version 2) Carrier Board

So far, I have done the following:

First, I tried to set the pin with jetson-io.py, but only “Configure Jetson Nano CSI Connector” was displayed and there was no pin setting item.

Next, I followed the tutorial for the A203 board to install JetPack version 4.6 and the .dtb file shown in “Install the carrier board driver”.

Then, to enable SPI communication, I added “spidev” to the last line of /etc/modules-load.d/modules.conf and rebooted.
I typed $ ls /dev/spi* in the terminal and saw the output below.
spidev0.0
spidev0.1
spidev1.0
spidev1.1

However, in the SPI loopback test connecting No.19 and No.21 of 40pin, reception was not possible.
This test program has been verified to work correctly with the Jetson Xavier NX Development kit.

According to the pin description document (A203 V2 pin description.pdf) on the product page, pin 19 is SPI0_MOSI_3.3V and pin 21 is SPI0_MISO_3.3V, so connecting these should enable transmission and reception.

Additionally, I did the following:

I followed the instructions in the NVIDIA forum answer at the URL below.

Modify those pins spi1__ to spi1 in “nvidia,function” like below.

spi1_mosi_pc0 {
                                nvidia,enable-input = <0x1>;
                                nvidia,pins = "spi1_mosi_pc0";
                                nvidia,tristate = <0x0>;
                                nvidia,function = "spi1";
                                nvidia,pull = <0x1>;
                        };

The procedure is as follows.

  1. Decompiled your driver (.dtb file) with Device Tree Compiler.
  2. I changed rsvd1 to spi1 in nvidia,function= “rsvd1”; in the .dts file.
  3. Recompiled the modified .dts file and converted it to a .dtb file.
  4. Overwritten the DTB partition on the Jetson Nano module to apply the changes.

However, in the SPI loopback test, I could not receive it.

And, I found a similar problem with another Seeed carrier board and tried the steps.
But SPI was not enabled.

So I contacted SeeedStudio technical support.

I received an answer to set the pins by executing config-by-pin.py and config-by-funcion.py from the command line according to the following page.
https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-3261/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/hw_setup_jetson_io.html%23wwpID0E0ED0HA

However, these scripts give the following output and appear to only allow configuration of the CSI connector.

user01@jetson:~$ sudo /opt/nvidia/jetson-io/config-by-pin.py
Header 1 [default]: Jetson Nano CSI Connector
  1: GND
  7: GND
 13: GND
 19: GND
 29: 3.3V
user01@jetson:~$
user01@jetson:~$ sudo /opt/nvidia/jetson-io/config-by-function.py -l all
Header 1 [default]: Jetson Nano CSI Connector
  No functions are supported.
user01@jetson:~$

In fact, I tried to generate a .dtb file to enable spi1, but it is outputting an error like below.

user01@jetson:~$ sudo /opt/nvidia/jetson-io/config-by-function.py -o dtb 1="spi1"
Traceback (most recent call last):
  File "/opt/nvidia/jetson-io/config-by-function.py", line 184, in <module>
    main()
  File "/opt/nvidia/jetson-io/config-by-function.py", line 167, in main
    dtbo = configure_jetson(jetson, args.out, header, funcs[idx])
  File "/opt/nvidia/jetson-io/config-by-function.py", line 81, in configure_jetson
    % (function, header))
NameError: Function spi1 is not supported on Jetson Nano CSI Connector!
user01@jetson:~$
user01@jetson:~$ sudo /opt/nvidia/jetson-io/config-by-function.py -o dtb 2="spi1"
Traceback (most recent call last):
  File "/opt/nvidia/jetson-io/config-by-function.py", line 184, in <module>
    main()
  File "/opt/nvidia/jetson-io/config-by-function.py", line 158, in main
    funcs = parse_function_args(args.functions, len(headers))
  File "/opt/nvidia/jetson-io/config-by-function.py", line 111, in parse_function_args
    raise IndexError("Invalid Header number %d!" % (idx + 1))
IndexError: Invalid Header number 2!
user01@jetson:~$

I sent these errors to tech support and they recommended I ask them on the NVIDIA forums, so I posted them here.

Do you know how to enable SPI from these scripts?

Dump the REG to confirm the configuration.

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi

Thank you for your reply.
The pin register values are shown below.

user01@jetson:~$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
Bank: 1 Reg: 0x70003050 Val: 0x0000e045 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e045 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e045 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e049 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e049 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006046 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006046 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006046 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006046 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006045 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 -> qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp
user01@jetson:~$ 

Looks like the REG dump is incorrect.
Please reference to the topic to confirm apply correct device tree.

Hello, @ShaneCCC

I would like to confirm which dtb file to modify and how to apply it.

As far as I have researched similar topics, SPI was enabled with the steps below.
If there are any mistakes, please point them out.

  1. Run the dmesg command on Jetson and the result shows that tegra210-p3448-0002-p3449-0000-b00.dts is used.
user01@jetson:~$ dmesg | grep -i kernel
[    0.000000] Kernel command line: tegraid=21.1.2.0.0 ddr_die=4096M@2048M section=512M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 console=ttyS0,115200n8 debug_uartport=lsport,4 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff780000 core_edp_mv=1075 core_edp_ma=4000 gpt  earlycon=uart8250,mmio32,0x70006000  root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1 quiet root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1 
[    0.000000] Memory: 3568468K/4159488K available (15358K kernel code, 2956K rwdata, 6692K rodata, 8640K init, 612K bss, 115884K reserved, 475136K cma-reserved)
[    0.000000] Virtual kernel memory layout:
[    0.001712] kmemleak: Kernel memory leak detector disabled
[    0.207791] DTS File Name: /dvs/git/dirty/git-master_linux/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0002-p3449-0000-b00.dts
[    0.321298] alternatives: patching kernel code
[    0.412364] DTS File Name: /dvs/git/dirty/git-master_linux/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0002-p3449-0000-b00.dts
[    0.542000] eventlib_kernel: keventlib is initialized, test id: 0
[    1.967953] KERNEL: PMC reset status reg: 0x0
[    2.013666] Freeing unused kernel memory: 8640K
user01@jetson:~$ 
  1. On the Ubuntu host computer, convert Linux_for_Tegra/kernel/dtb/tegra210-p3448-0002-p3449-0000-b00.dtb to a .dts file using the device tree compiler.
$ dtc -I dtb -O dts -o ./extracted.dts ./tegra210-p3448-0002-p3449-0000-b00.dtb
  1. Rewrite the 5 items starting with “spi1_” in the dts file as follows.
			spi1_mosi_pc0 {
				nvidia,pins = "spi1_mosi_pc0";
				nvidia,function = "spi1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_miso_pc1 {
				nvidia,pins = "spi1_miso_pc1";
				nvidia,function = "spi1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_sck_pc2 {
				nvidia,pins = "spi1_sck_pc2";
				nvidia,function = "spi1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_cs0_pc3 {
				nvidia,pins = "spi1_cs0_pc3";
				nvidia,function = "spi1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};

			spi1_cs1_pc4 {
				nvidia,pins = "spi1_cs1_pc4";
				nvidia,function = "spi1";
				nvidia,pull = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,enable-input = <0x1>;
			};
  1. Convert the dts file to a dtb file using the device tree compiler.
$ dtc -I dts -O dtb -o ./tegra210-p3448-0002-p3449-0000-b00.dtb ./extracted.dts
  1. Overwrite Linux_for_Tegra/kernel/dtb/tegra210-p3448-0002-p3449-0000-b00.dtb with the dtb file compiled in the previous step.

  2. Check the partition name on Jetson. It shows that there is a partition named “DTB”.

user01@jetson:~$ ls -al /dev/disk/by-partlabel/
total 0
drwxr-xr-x 2 root root 380 10月  5 16:16 .
drwxr-xr-x 8 root root 160 10月  5 16:16 ..
lrwxrwxrwx 1 root root  15 10月  5 16:16 APP -> ../../mmcblk0p1
lrwxrwxrwx 1 root root  16 10月  5 16:16 BMP -> ../../mmcblk0p10
lrwxrwxrwx 1 root root  15 10月  5 16:16 DTB -> ../../mmcblk0p2
lrwxrwxrwx 1 root root  15 10月  5 16:16 DTB-1 -> ../../mmcblk0p6
lrwxrwxrwx 1 root root  15 10月  5 16:16 EKS -> ../../mmcblk0p4
lrwxrwxrwx 1 root root  15 10月  5 16:16 EKS-1 -> ../../mmcblk0p8
lrwxrwxrwx 1 root root  16 10月  5 16:16 kernel-bootctrl -> ../../mmcblk0p14
lrwxrwxrwx 1 root root  16 10月  5 16:16 kernel-bootctrl_b -> ../../mmcblk0p15
lrwxrwxrwx 1 root root  15 10月  5 16:16 LNX -> ../../mmcblk0p5
lrwxrwxrwx 1 root root  15 10月  5 16:16 LNX-1 -> ../../mmcblk0p9
lrwxrwxrwx 1 root root  16 10月  5 16:16 recovery -> ../../mmcblk0p12
lrwxrwxrwx 1 root root  16 10月  5 16:16 recovery-dtb -> ../../mmcblk0p13
lrwxrwxrwx 1 root root  16 10月  5 16:16 RECROOTFS -> ../../mmcblk0p16
lrwxrwxrwx 1 root root  16 10月  5 16:16 RP4 -> ../../mmcblk0p11
lrwxrwxrwx 1 root root  15 10月  5 16:16 TOS -> ../../mmcblk0p3
lrwxrwxrwx 1 root root  15 10月  5 16:16 TOS-1 -> ../../mmcblk0p7
lrwxrwxrwx 1 root root  16 10月  5 16:16 UDA -> ../../mmcblk0p17
user01@jetson:~$ 
  1. Execute the following command on the host computer to write to the DTB partition and apply the device tree configuration.
username@pcname:~/username/Jetson/R32.6.1/Linux_for_Tegra$ sudo ./flash.sh -r -k DTB -d ./kernel/dtb/tegra210-p3448-0002-p3449-0000-b00.dtb jetson-nano-emmc mmcblk0p1
  1. Reboot Jetson.

Thank you,

Dump it from the Nano runtime to confirm.
If doesn’t as your modification try flash without “-k DTB”

sudo dtc -I fs -O dts -o extracted_proc.dts /proc/device-tree

Hello, @ShaneCCC

To get straight to the point, I was able to enable the SPI pins on my A203 carrier board using Jetson Linux R32.7.2.
It was important to flash without “-k DTB” and use R32.7.2.

sudo dtc -I fs -O dts -o extracted_proc.dts /proc/device-tree

I checked the /proc/device-tree when I flashed with the “-k DTB” option.
It seems that there were multiple settings with the same name spi1_***, causing a conflict.
The probable cause is that an incorrect setting was left in the process of trial and error.

On the other hand, the device tree file when flashing without -k DTB had unique settings named spi1_***.

Also, R32.6.1 seems to have a problem with the SPI pin setting, and the pin was not enabled simply by rewriting the spi1_*** item in the .dtb file.

So I used R32.7.2 to enable the pin.

Just in case, the register dump at this time (R32.7.2) is shown below.

user01@jetson:~$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e044 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e044 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006016 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006016 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006016 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006016 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006015 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 -> qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp
user01@jetson:~$ 

user01@jetson:~$ sudo cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 04 00 00 000000
 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 00 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 00 00 00 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 00 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 03 02 00 00 000000
 J: 2:1 00 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 80 80 00 00 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 02 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 30 00 60 606000
 Y: 6:0 02 00 00 02 00 00 000000
 Z: 6:1 0e 08 00 06 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 92 80 80 00 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000
user01@jetson:~$ 

Then install spidev.
Enable spidev from /etc/modules-load.d/modules.conf and reboot.

tegra_gpio changes as follows

user01@jetson:~$ sudo cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 04 00 00 000000
 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 00 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 00 00 00 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 00 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 07 03 02 00 00 000000
 J: 2:1 00 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 80 80 00 00 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 02 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 70 00 60 606000
 Y: 6:0 02 00 00 02 00 00 000000
 Z: 6:1 0e 08 00 06 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 92 80 80 00 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000
user01@jetson:~$

Thank you very much.

You can also modify the /boot/extlinux/extlinux.conf for customized dtb instead of flash.sh command

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