How to init the drivers for all I2C buses synchronized?

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
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1

Hi,

I am trying to write an i2c driver based on i2c@31e0000 controller.
After System boots up, I can see the driver launched after i2c@31e0000 is added to iommu group 2, but the launched time is too late.
I noticed that it might be delayed because i2c@31e0000 is initialized too late. (see below capture)

==========
[ 3.080283] i2c /dev entries driver
[ 3.083599] tegra-i2c 3160000.i2c: Adding to iommu group 2
[ 3.089339] tegra-i2c c240000.i2c: Adding to iommu group 2
[ 3.094759] tegra-i2c 3180000.i2c: Adding to iommu group 2
[ 3.100095] tegra-i2c 3190000.i2c: Adding to iommu group 2
[ 3.105438] tegra-i2c 31c0000.i2c: Adding to iommu group 2
[ 3.110912] tegra-i2c c250000.i2c: Adding to iommu group 2
[ 3.116384] tegra-i2c 31b0000.i2c: Adding to iommu group 2
[ 9.870902] tegra-i2c 31e0000.i2c: Adding to iommu group 2

Is it possible to initialize i2c@31e0000 at the same time as other I2C buses?

The Jetson version I used is 35.2.1.

4

Hi

Any updates?

5

Looks like it’s r35 release regression. Doesn’t have problem on r32 release though.

7

Hi Shane

Then, do you have any suggestions?

8

I am checking it will update once get any.

Thanks

9

Hi Shane

Do you have any updates now?

10

Hi,
Suppose the root cause should be below. But I don’t have any solution now.

i2c@31e0000 has the below pinctrl dependency to take care of converting dp_aux_ch3 port into general purpose I2C.

i2c@31e0000{
       pinctrl-names = "default";
        pinctrl-0 = <0x00000043>;
}


dpaux@155F0000 {
            compatible = "nvidia,tegra194-dpaux3-padctl";
            pinmux@0 {
                phandle = <0x00000043>;
                dpaux3_pins {
                    pins = "dpaux3-3";
                    function = "i2c";
                };
            };
};

So i2c@31e0000 probe has dependency on below driver probe and the execution of tegra_dpaux_pinctrl_set_mode() through pinctrl framework. And below driver probe might defer if BPMP-FW is not available at the time of its execution.

11

Hi Shane,

Do you have any solutions now?

12

Suppose it’s kernel regression cause the behavior change.
What’s cause your problem for this behavior?

13

Check whether modifying linux initcall priorities can help in initialization order

14

Hi Shane

I have a DCDC controlled by this I2C channel, and it needs to output specified power to some components dependent on PCIe.
Currently, I always see the PCIe drivers launched before DCDC output power.

15

I would suggest change the PCIE drivers order to later.

16

Hi Shane

You mean to push 141a0000.pcie to later?

[ 7.689589] tegra194-pcie 141a0000.pcie: Adding to iommu group 10
[ 7.696096] tegra194-pcie 141a0000.pcie: host bridge /pcie@141a0000 ranges:
[ 7.696495] tegra194-pcie 141a0000.pcie: IO 0x003a100000…0x003a1fffff → 0x003a100000
[ 7.696924] tegra194-pcie 141a0000.pcie: MEM 0x1c00000000…0x1f3fffffff → 0x1c00000000
[ 7.697332] tegra194-pcie 141a0000.pcie: MEM 0x1f40000000…0x1fffffffff → 0x0040000000
[ 8.806765] tegra194-pcie 141a0000.pcie: Phy link never came up
[ 8.807574] tegra194-pcie 141a0000.pcie: PCI host bridge to bus 0005:00
[ 8.807828] pci_bus 0005:00: root bus resource [bus 00-ff]
[ 8.807988] pci_bus 0005:00: root bus resource [io 0x300000-0x3fffff] (bus address [0x3a100000-0x3a1fffff])
[ 8.808295] pci_bus 0005:00: root bus resource [mem 0x1c00000000-0x1f3fffffff pref]
[ 8.808618] pci_bus 0005:00: root bus resource [mem 0x1f40000000-0x1fffffffff] (bus address [0x40000000-0xffffffff])
[ 8.809046] pci 0005:00:00.0: [10de:1ad0] type 01 class 0x060400
[ 8.809542] pci 0005:00:00.0: PME# supported from D0 D3hot D3cold
[ 8.834672] pci 0005:00:00.0: PCI bridge to [bus 01-ff]
[ 8.834963] pci 0005:00:00.0: Max Payload Size set to 256/ 256 (was 256), Max Read Rq 512
[ 8.837170] pcieport 0005:00:00.0: Adding to iommu group 10
[ 8.838995] pcieport 0005:00:00.0: PME: Signaling with IRQ 30
[ 8.840596] pcieport 0005:00:00.0: AER: enabled with IRQ 30
[ 8.842271] pci_bus 0005:01: busn_res: [bus 01-ff] is released
[ 8.843344] pci 0005:00:00.0: Removing from iommu group 10
[ 8.843707] pci_bus 0005:00: busn_res: [bus 00-ff] is released
[ 9.511192] tegra-i2c 31e0000.i2c: Adding to iommu group 2

17

Suggest build your PCIE device driver as loadable module(.ko) to load after boot to system.

18

Hi Shane,

Thanks for your suggestions.
I will try it, but one question is that the DCDC can not power on the PCIe device before I2C channel is generated.
It means that Tegra PCIe driver can not find the device when scanning before I2C.
Then even delay the PCIe device driver by insert .ko, does it work?

20

For this case I would suggest move to others I2C bus.

Thanks

22

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