Is I2C5_CLK/DATA, (i2c9 i2c@31e0000) usable?


I am designing my own carrier for xavier. I have an IO expander (PCA9539) connected to I2C5_CLK/DATA (pin A53/C53). It is the i2c controller - i2c9 (i2c@31e0000). But PCA9539 is not detected. We have the same PCA9539 connected to I2C1_CLK/DATA, this one works.

I checked OEM and pinmux spreadsheet. I2C5_CLK/DATA (pin A53/C53) can be muxed in DP_AUX_CH3_P/N function. But it should be default set to I2C function.

However, I did a test on that pinmux spreadsheet by switch them in DP_AUX_CH3_P/N function and convert it in pinmux .cfg file. I realized that there is NO change in pinmux .cfg file.

I also looked through pinctrl-tegra194.c driver, it seems there is no pinmux function setting for i2c9.

Is I2C5_CLK/DATA, (i2c9 i2c@31e0000) really in I2C mode, and usage?

Also, note that I am using Jetpack-4.4.


Suppose are default enable as i2c function due to devkit have i2c-mux chip pca9546 on this bus.


Thanks for your reply.

I actually don’t see i2c-mux on devkit carrier schematic. Is the i2c-mux on devkit carrier?

I saw the schematic, It is the I2C_GP5_CLK/DAT (pin A53/C53), go thru the level shifter (FXMA2102L8X), then connected to 40PIN header - J30 (on pin 3 and pin 5).

Have you verified these two I2C pins on NVIDIA side?



I saw device-tree binding for i2c-mux chip pca9546 in “tegra194-super-module-e2614-p2888-0000.dtsi” which is included by “tegra194-p2888-0001-p2822-0000-common.dtsi”.

What is this “super-module-e2614”? Is it plugged in devkit carrier (thru headers)? Or the new hw revision of carrier?



I double checked by changing the pinmux of I2C5_CLK/DATA (pin A53/C53) to DP_AUX_CH3_P/N function, and changing them back to I2C5_CLK/DATA function. And I can 100% confirm that the generated dtsi files are the same. And the converted pinmux .cfg files are the same as well.

From pinmux perspective, how come I2C and DP_AUX function gives the same dtsi and pinmux .cfg file?
How can I use devmem2 command to verify the pinmux settings for I2C5_CLK/DATA are really set to i2c?

I did some investigation on device-tree. It looks like I2C5 pinmux setting are set by “nvidia,tegra194-dpaux3-padctl” driver!

Here is the section that I am missing in my device-tree file:

host1x {
		dpaux@155F0000 {
			status = "okay";
			compatible = "nvidia,tegra194-dpaux3-padctl";
			/delete-property/ power-domains;
			dpaux_default: pinmux@0 {
				dpaux3_pins {
					pins = "dpaux3-3";
					function = "i2c";

And then in the I2C5 node, it has to set pinctrl to reference it:

i2c@31e0000 {
		pinctrl-names = "default";
		pinctrl-0 = <&dpaux_default>;

I think adding these in device-tree will make it to work.

In my carrier, I don’t have any display nor hdmi etc. So, I disabled all below in my device-tree:

I am not 100% sure that enabling nvidia,tegra194-dpaux3-padctl on dpaux@155F0000 will cause any issue or not. I will test it tomorrow at work.

Can we add this pinmux setting in pinmux .cfg so that we can set it in i2c mode in pinmux MB1 CFG?


These pin didn’t control by the pinmux so you didn’t see any different for it.
Yes, please enable nvidia,tegra194-dpaux3-padctl on dpaux@155F0000

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I got a different error this time:

[    3.428873] tegra-i2c 31e0000.i2c: no acknowledge from address 0x74
[    3.428908] pca953x 8-0074: failed reading register
[    3.429049] pca953x: probe of 8-0074 failed with error -121

I forgot to paste previous error, the previous error was:

[   11.117765] tegra-i2c 31e0000.i2c: pio timed out addr: 0x74 tlen:28 rlen:4
[   11.117963] tegra-i2c 31e0000.i2c: --- register dump for debugging ----
[   11.118128] tegra-i2c 31e0000.i2c: I2C_CNFG - 0x22c00
[   11.118236] tegra-i2c 31e0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[   11.118389] tegra-i2c 31e0000.i2c: I2C_FIFO_CONTROL - 0x0
[   11.118501] tegra-i2c 31e0000.i2c: I2C_FIFO_STATUS - 0x800080
[   11.118641] tegra-i2c 31e0000.i2c: I2C_MST_FIFO_CONTROL - 0x70000
[   11.118766] tegra-i2c 31e0000.i2c: I2C_MST_FIFO_STATUS - 0x7c0000
[   11.118919] tegra-i2c 31e0000.i2c: I2C_MST_PACKET_TRANSFER_CNT - 0x0
[   11.119053] tegra-i2c 31e0000.i2c: I2C_INT_MASK - 0x7d
[   11.119182] tegra-i2c 31e0000.i2c: I2C_INT_STATUS - 0x2
[   11.119295] tegra-i2c 31e0000.i2c: i2c transfer timed out addr: 0x74
[   11.119483] pca953x 8-0074: failed reading register

What register shall we devmem2 on it to make sure pins are in i2c mode?


Could you probe the i2c it any waves when do the i2cdetect for this bus.


We probed the I2C data and clock. pinmux is correct. We found we made a mistake where clk and data are swapped. It was a mistake in our hw.


Great to know it solve.

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