uses i2c6 (dp0_aux_ch)

[atien.hsieh]

Hi,

I had used dp0_aux connecting an i2c device for HW configuration.

Both sor and sor1 in device tree were disabled. (to disable HDMI and DP)
And both dpaux@155c0000 and dpaux@15040000 were disabled, too.

I checked the TRM for dp0_aux, so I put the device in i2c@31b0000 for i2c6 controlling, but it shows the i2c error message.

i2c@31b0000 {
lm3697@36 {
compatible = “ti,lm3697”;

[ 4.896321] tegra-i2c 31b0000.i2c: pio xfer timed out addr: 0x36
[ 4.902357] tegra-i2c 31b0000.i2c: — register dump for debugging ----
[ 4.908990] tegra-i2c 31b0000.i2c: I2C_CNFG - 0x22c00
[ 4.914058] tegra-i2c 31b0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 4.920691] tegra-i2c 31b0000.i2c: I2C_FIFO_CONTROL - 0xe0
[ 4.926195] tegra-i2c 31b0000.i2c: I2C_FIFO_STATUS - 0x800040
[ 4.931959] tegra-i2c 31b0000.i2c: I2C_INT_MASK - 0x7d
[ 4.937114] tegra-i2c 31b0000.i2c: I2C_INT_STATUS - 0x0
[ 4.942359] tegra-i2c 31b0000.i2c: i2c transfer timed out addr: 0x36

Thanks.

[Trumany]

Hi, DP0_AUX_CH is used for DP0 default, and no pull-up resistors connected. If you want to use it as I2C, the pull-up resistors are needed.

[atien.hsieh]

Hi Trumany,

I confirm that we had 10KOHM pull up resistors.
I also check the waveform, both SCL and SDA are 1.8V high level.
Are there any idea which related to DP in driver or device tree I have to shut them down for i2c6 access?

Below shows the note in OEM design guide
Note: For I2C interfaces that are pulled up to 1.8V, disable the E_OD_HV option for these pads. For I2C interfaces that are pulled up to 3.3V, enable the E_OD_HV option. The Open Drain option is selected in the Pinmux registers.

Right now, we’re using 1.8V.
Can you help to tell me how do I disable E_OD_HV?

Thanks

[Trumany]

Please refer to latest version OEM DG, it is said : For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers.

So you can find the pinmux register in TRM and disable E_IO_HV. This topic mentioned the E_IO_HV setting, [url]https://devtalk.nvidia.com/default/topic/1024798/with-jetpack3-1-aon-gpios-paa03-06-can-no-longer-be-configured-with-io-high-voltage/?offset=2[/url]

[atien.hsieh]

Hi Trumany,

I used the pin name defined in pinmux excel file to change the io-high-voltage settings for i2c6-scl and i2c6-sda as below in device tree.
But the pin-control driver does not accpet the pin name.

pinmux@2430000 {
common {
i2c6_scl {
nvidia,pins = “dp_aux_ch0_p”;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
};
i2c6_sda {
nvidia,pins = “dp_aux_ch0_n”;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
};

[ 0.233915] tegra186-pinctrl 2430000.pinmux: does not have pin group dp_aux_ch0_p
[ 0.233972] tegra186-pinctrl 2430000.pinmux: could not map group config for dp_aux_ch0_p"
[ 0.234055] tegra186-pinctrl 2430000.pinmux: does not have pin group dp_aux_ch0_n
[ 0.234088] tegra186-pinctrl 2430000.pinmux: could not map group config for dp_aux_ch0_n"

Thanks

[atien.hsieh]

Hi Trumany,

For TRM, I searched E_IO_HV in chapter8 (pinmuxing) and found below pads supported E_IO_HV control
I can find the pads DP_AUX_CH0_HPD_0 and DP_AUX_CH1_HPD_0 support E_IO_HV control
But the pads I used were not hot plug pin.
Does it mean I can have the 1.8v settings for all SCL, SDA and HPD if configured PADCTL_EDP_DP_AUX_CH0_HPD_0 to nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>?
Is my understanding correct?

PADCTL_AO_GEN8_I2C_SDA_0
PADCTL_AO_GEN8_I2C_SCL_0
PADCTL_AO_GPIO_SEN8_0
PADCTL_AO_GPIO_SEN9_0
PADCTL_CAM_CAM_I2C_SDA_0
PADCTL_CAM_CAM_I2C_SCL_0
PADCTL_CONN_GEN1_I2C_SCL_0
PADCTL_CONN_GEN1_I2C_SDA_0
PADCTL_EDP_GPIO_EDP2_0
PADCTL_EDP_DP_AUX_CH0_HPD_0
PADCTL_EDP_DP_AUX_CH1_HPD_0
PADCTL_EDP_HDMI_CEC_0
PADCTL_PEX_CTL_PEX_L2_CLKREQ_N_0
PADCTL_PEX_CTL_PEX_L1_RST_N_0
PADCTL_PEX_CTL_PEX_L0_CLKREQ_N_0
PADCTL_PEX_CTL_PEX_L0_RST_N_0
PADCTL_PEX_CTL_PEX_L2_RST_N_0
PADCTL_SYS_PWR_I2C_SCL_0
PADCTL_SYS_PWR_I2C_SDA_0
PADCTL_UART_GEN7_I2C_SCL_0
PADCTL_UART_GEN7_I2C_SDA_0
PADCTL_UART_GEN9_I2C_SDA_0
PADCTL_UART_USB_VBUS_EN1_0

Thanks

[ShaneCCC]

You can find the correct name from this file.

…/kernel/t18x/drivers/pinctrl/pinctrl-tegra186.c

"dp_aux_ch0_hpd_pp0",
	"dp_aux_ch1_hpd_pp1",

[atien.hsieh]

Hi,

I try below in device tree
And there’s no error from pinctrl driver now
But I still have the error message from i2c driver
Can you teach how I can read back the register of PADCTL_EDP_DP_AUX_CH0_HPD_0 to confirm E_IO_HV setting
If E_IO_HV bit is disabled, and it might not related to E_IO_HV setting
Thanks

pinmux@2430000 {
common {
i2c5_pads {
nvidia,pins = “dp_aux_ch0_hpd_pp0”;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
};

[ 4.896321] tegra-i2c 31b0000.i2c: pio xfer timed out addr: 0x36
[ 4.902357] tegra-i2c 31b0000.i2c: — register dump for debugging ----
[ 4.908990] tegra-i2c 31b0000.i2c: I2C_CNFG - 0x22c00
[ 4.914058] tegra-i2c 31b0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 4.920691] tegra-i2c 31b0000.i2c: I2C_FIFO_CONTROL - 0xe0
[ 4.926195] tegra-i2c 31b0000.i2c: I2C_FIFO_STATUS - 0x800040
[ 4.931959] tegra-i2c 31b0000.i2c: I2C_INT_MASK - 0x7d
[ 4.937114] tegra-i2c 31b0000.i2c: I2C_INT_STATUS - 0x0
[ 4.942359] tegra-i2c 31b0000.i2c: i2c transfer timed out addr: 0x36

[atien.hsieh]

Hi Shane,

can you help to confirm about setting to 1.8V for “dp_aux_ch0_p” and “dp_aux_ch0_n” for i2c6 usage?

1. Does it mean I can have the 1.8V settings for dp_aux_ch0_p and dp_aux_ch0_n if I configure “nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>” for “dp_aux_ch0_hpd_pp0” like below?

pinmux@2430000 {
common {
i2c5_pads {
nvidia,pins = “dp_aux_ch0_hpd_pp0”;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
};
};

2. Should I fill the “nvidia,function” for i2c6 usage?
   Is below workable?

pinmux@2430000 {
common {
i2c5_pads {
nvidia,function = “i2c”;
nvidia,pins = “dp_aux_ch0_hpd_pp0”;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
};
};

Thanks

[atien.hsieh]

Hi Trumany,

We have tried both 1.8V and 3.3V pull up resistors for using i2c6.
I think it might relate to others for such error message.
Can you help to figure out what we have done if we want to use i2c6 on TX2?
We can check your instruction item by item to fix it.
Thanks.

[ 4.896321] tegra-i2c 31b0000.i2c: pio xfer timed out addr: 0x36
[ 4.902357] tegra-i2c 31b0000.i2c: — register dump for debugging ----
[ 4.908990] tegra-i2c 31b0000.i2c: I2C_CNFG - 0x22c00
[ 4.914058] tegra-i2c 31b0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x10001
[ 4.920691] tegra-i2c 31b0000.i2c: I2C_FIFO_CONTROL - 0xe0
[ 4.926195] tegra-i2c 31b0000.i2c: I2C_FIFO_STATUS - 0x800040
[ 4.931959] tegra-i2c 31b0000.i2c: I2C_INT_MASK - 0x7d
[ 4.937114] tegra-i2c 31b0000.i2c: I2C_INT_STATUS - 0x0
[ 4.942359] tegra-i2c 31b0000.i2c: i2c transfer timed out addr: 0x36

[ShaneCCC]

The following patch can switch dpaux0 to I2C mode. Please put some message to make sure the this function is be called.

diff --git a/drivers/video/tegra/dc/hdmi2.0.c b/drivers/video/tegra/dc/hdmi2.0.c
index 2f1ade2..6059712 100644
--- a/drivers/video/tegra/dc/hdmi2.0.c
+++ b/drivers/video/tegra/dc/hdmi2.0.c
@@ -2402,3 +2402,16 @@ struct tegra_dc_out_ops tegra_dc_hdmi2_0_ops = {
        .set_hdr = tegra_dc_hdmi_set_hdr,
        .postpoweron = tegra_dc_hdmi_postpoweron,
 };
+
+static __init int dpaux_switch_i2c_mode(void)
+{
+       struct tegra_hdmi *hdmi = dc_hdmi;
+       if (hdmi) {
+               tegra_hdmi_get(hdmi->dc);
+               tegra_dpaux_config_pad_mode(hdmi->dc,
+                       TEGRA_DPAUX_INSTANCE_0, TEGRA_DPAUX_PAD_MODE_I2C);
+               tegra_hdmi_put(hdmi->dc);
+       }
+       return 0;
+}
+late_initcall(dpaux_switch_i2c_mode);

[atien.hsieh]

Hi Shane,

Two question for what you mentioned!

1:
If I turned on HDMI to dp_hdmi_0, how I can use i2c6 by other device driver?
The i2c bus will be used as DDC, isn’t it?

2:
I’m using R28.1.0 code base.
The function in R28.1.0 only has 2 arguments.

void tegra_dpaux_config_pad_mode(struct tegra_dc_dpaux_data *dpaux,
enum tegra_dpaux_pad_mode mode)

Thanks

[ShaneCCC]

@atien

1. HDMI is “DP1_AUX_CH”
2. This patch only to set it as i2c mode. Would you reference to r24.2.1 to see what register this patch going to set and make a patch for r28.1.

[atien.hsieh]

Hi Shane,

Thanks, I will check how downloads r24 to study the patch about setting i2c mode on dpaux0 pads.

There’re 2 finds to feedback.

I found there’s a driver showed below which was using for switching between i2c and dp_aux mode.
It’s much convenient for using i2c6 but disabled sor and hdmi-dp-0.
I had tried to build-in the driver and it worked for switching to the i2c mode.
However, it still have the “pio xfer timed out” issue on i2c6 even this driver switched dpaux0 to i2c mode before the i2c TX started.

driver:
pinctrl-tegra186-dpaux.c

device tree:
host1x {
dpaux@155c0000 {
compatible = “nvidia,tegra186-dpaux-padctl”;
status = “okay”;
reg = <0x0 0x155c0000 0x0 0x00040000>;
pinctrl-names = “default”;
pinctrl-0 = <&dpaux_default>;
dpaux_default: pinmux@0 {
dpaux0_pins {
pins = “dpaux-0”;
function = “i2c”;
};
};
};

2. above driver and the below functions in dpaux.c update below registers for configuring i2c mode on dpaux0.

static inline void tegra_dpaux_config_pad_mode(struct tegra_dc_dpaux_data *dpaux, enum tegra_dpaux_pad_mode mode);
REG: DPAUX_HYBRID_PADCTL_0
BIT15: I2C_SDA_INPUT_RCV (0=DIS, 1=EN)
BIT14: I2C_SCL_INPUT_RCV (0=DIS, 1=EN)
BIT0: AUX (0=AUX, 1=I2C)

static inline void _tegra_dpaux_pad_power(struct tegra_dc_dpaux_data *dpaux, bool on);
REG: DPAUX_HYBRID_SPARE_0
BIT1: RCV_33_18_SEL (0=SEL_1_8V, 1=SEL_3_3V)
BIT0: PAD_PWR (0=POWERUP, 1=POWERDOWN)

[ShaneCCC]

Could you check the 0x155c0124 by devmem2 to see what the different before and after you add the dpaux@155c0000 in DT.

155c0124: DPAUX_HYBRID_PADCTL_0                                   = 0x00002462 //
          I2C_SDA_INPUT_RCV                                       = 0x00000000 // [15:15] DISABLE [DISABLE=0,ENABLE=1]
          I2C_SCL_INPUT_RCV                                       = 0x00000000 // [14:14] DISABLE [DISABLE=0,ENABLE=1]
          AUX_CMH                                                 = 0x00000002 // [13:12] V1_10 [V0_10=0,V0_55=1,V1_10=2,V1_60=3]
          AUX_DRVZ                                                = 0x00000004 // [10:08] OHM_56_49 [OHM_38_10=7,OHM_43_91=6,OHM_47_15=5,OHM_51_53=3,OHM_56_49=4,OHM_62_94=2,OHM_70_12=1,OHM_93_37=0]
          AUX_DRVI                                                = 0x00000018 // [07:02] I12_00 [I00_00=0,I07_17=1,I07_81=4,I08_02=5,I08_23=6,I08_44=7,I08_65=8,I08_86=9,I09_07=10,I09_28=11,I09_49=12,I09_70=13,I09_91=14,I10_12=15,I10_33=16,I10_54=17,I10_75=18,I10_96=19,I11_17=20,I11_37=21,I11_58=22,I11_79=23,I12_00=24,I12_20=25,I12_41=26,I12_62=27,I12_82=28,I13_03=29,I13_23=30,I13_44=31,I13_64=32,I13_84=33,I14_04=34,I14_25=35,I14_45=36,I14_65=37,I14_85=38,I15_05=39,I15_24=40,I15_44=41,I15_63=42,I15_83=43,I16_02=44,I16_21=45,I16_40=46,I16_59=47,I16_78=48,I16_96=49,I17_14=50,I17_32=51,I17_49=52,I17_66=53,I17_82=54,I17_98=55,I18_13=56,I18_28=57,I18_43=58,I18_56=59,I18_69=60,I18_82=61,I18_94=62,I19_05=63,V07_38=2,V07_59=3]
          AUX_INPUT_RCV                                           = 0x00000001 // [01:01] ENABLE [DISABLE=0,ENABLE=1]
          MODE                                                    = 0x00000000 // [00:00] AUX [AUX=0,I2C=1]
          I2C_SDA_INPUT_RCV                                       = 0x00000000 // [15:15] DISABLE [DISABLE=0,ENABLE=1]
          I2C_SCL_INPUT_RCV                                       = 0x00000000 // [14:14] DISABLE [DISABLE=0,ENABLE=1]
          AUX_CMH                                                 = 0x00000002 // [13:12] V1_10 [V0_10=0,V0_55=1,V1_10=2,V1_60=3]
          AUX_DRVZ                                                = 0x00000004 // [10:08] OHM_56_49 [OHM_38_10=7,OHM_43_91=6,OHM_47_15=5,OHM_51_53=3,OHM_56_49=4,OHM_62_94=2,OHM_70_12=1,OHM_93_37=0]
          AUX_DRVI                                                = 0x00000018 // [07:02] I12_00 [I00_00=0,I07_17=1,I07_81=4,I08_02=5,I08_23=6,I08_44=7,I08_65=8,I08_86=9,I09_07=10,I09_28=11,I09_49=12,I09_70=13,I09_91=14,I10_12=15,I10_33=16,I10_54=17,I10_75=18,I10_96=19,I11_17=20,I11_37=21,I11_58=22,I11_79=23,I12_00=24,I12_20=25,I12_41=26,I12_62=27,I12_82=28,I13_03=29,I13_23=30,I13_44=31,I13_64=32,I13_84=33,I14_04=34,I14_25=35,I14_45=36,I14_65=37,I14_85=38,I15_05=39,I15_24=40,I15_44=41,I15_63=42,I15_83=43,I16_02=44,I16_21=45,I16_40=46,I16_59=47,I16_78=48,I16_96=49,I17_14=50,I17_32=51,I17_49=52,I17_66=53,I17_82=54,I17_98=55,I18_13=56,I18_28=57,I18_43=58,I18_56=59,I18_69=60,I18_82=61,I18_94=62,I19_05=63,V07_38=2,V07_59=3]
          AUX_INPUT_RCV                                           = 0x00000001 // [01:01] ENABLE [DISABLE=0,ENABLE=1]
          MODE                                                    = 0x00000000 // [00:00] AUX [AUX=0,I2C=1]

[atien.hsieh]

Hi Shane,

Finally, we can access i2c-6 under both HDMI and DP off conditions.
The 0x155c0124 must be 0x0000E463 and it’s okay to access i2c-6.
Below shows the device tree we modified finally.
Thanks.

host1x {
	nvdisplay@15200000 {
		status = "okay";
	};

	nvdisplay@15210000 {
		status = "disabled";
	};

	nvdisplay@15220000 {
		status = "disabled";
	};

	sor {
		status = "disabled";
	};

	sor1 {
		status = "disabled";

		hdmi-display {
			status = "disabled";
		};

		dp-display {
			status = "disabled";
		};
	};

	dsi {
		status = "okay";

		panel-t-wuxga-8-0 {
			status = "okay";
		};
	};

	dpaux@15040000 {
		status = "disabled";
	};

	dpaux@155c0000 {
		compatible = "nvidia,tegra186-dpaux-padctl";
		status = "okay";
		reg = <0x0 0x155c0000 0x0 0x00040000>;

		interrupts = <0 159 0x4>;
		clocks = <&clk32k_in>,
			 <&tegra_car TEGRA186_CLK_DPAUX>,
			 <&tegra_car TEGRA186_CLK_PLLDP>;
		clock-names = "clk32k_in", "dpaux", "plldp";
		resets = <&tegra_car TEGRA186_RESET_DPAUX>;
		reset-names = "dpaux";
		///power-domains = <&disa_pd>;

		pinctrl-names = "default";
		pinctrl-0 = <&dpaux_default>;
		dpaux_default: pinmux@0 {
			dpaux0_pins {
				pins = "dpaux-0";
				function = "i2c";
			};
		};
	};
};

[ShaneCCC]

Well done and thanks for sharing your experience/code here.

[randyzhg]

Hi,

We are actually trying to do this exact thing. We want to use dp0_aux_ch+ and dp0_aux_ch- as i2c pins. After reading the previous posts and the accepted answer I’m still a little bit confused as what exactly needs to change. For example, what changes were made to the pinctrl-tegra186-dpaux.c driver? Or do you only need to make changes in the device tree to make it work?

Thanks

[ShaneCCC]

I think the key point is “The 0x155c0124 must be 0x0000E463”

[atien.hsieh]

Yes, it’s true. The correct register setting is the most important thing for the firmware programming.

To randyzhg,
I had only modified the device tree and then I could access the i2c-6.

Does you hardware design use DP or HDMI?

If so, I think that you can’t go it like my way. The register will be overwritten by DP or HDMI driver again!