Orin nano: muxing DP1_AUX as I2C [continuation]

This is a continuation of this previous ticket: Orin nano: muxing DP1_AUX as I2C

Summary:

  • goal: have I2C functionality on Orin Nano on pins 98/100
  • last reply from Nvidia: use the pinmux spreadsheet. But this is not effective since selecting I2C6 instead of DP_AUX_CH0 does not lead to any change in the generated DT files.

There are plenty of similar posts around, but for different platforms (TK1, TX1, TX2, Xavier NX and Xavier AGX).
Could you please share the procedure for the Orin Nana platform?

For reference, this is the DTS edit I tried:

i2c@31b0000 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&dpaux_default>;
};
host1x@13e00000 {
	dpaux@155c0000 {
		status = "okay";
		compatible = "nvidia,tegra194-misc-dpaux-padctl";
		reg = <0x0 0x155C0000 0x0 0xFFFF>;
		dpaux_default: pinmux@0 {
			dpaux0_pins {
				pins = "dpaux-0";
				function = "i2c";
			};
		};
	};
};

Note the use of nvidia,tegra194-misc-dpaux-padctl since this this is what is referenced under kernel/nvidia/drivers/pinctrl/pinctrl-tegra234-dpaux.c under the .compatible field.

But this fails at boot:

[    2.624869] tegra-i2c 31b0000.i2c: Adding to iommu group 2
[    2.624963] **************************************
[    2.625137] tegra-i2c 31c0000.i2c: Adding to iommu group 2
[    2.625195] CPU:0, Error:cbb-fabric, Errmon:2
[    2.625201] 	  Error Code		: TIMEOUT_ERR
[    2.625360] tegra-i2c c250000.i2c: Adding to iommu group 2
[    2.625414] 	  Overflow		: Multiple TIMEOUT_ERR
[    2.625550] tegra-i2c 31e0000.i2c: Adding to iommu group 2
[    2.625628] 
[    2.625883] 	  Error Code		: TIMEOUT_ERR
[    2.625972] 	  MASTER_ID		: CCPLEX
[    2.626048] 	  Address		: 0x155c4000
[    2.626133] 	  Cache			: 0x1 -- Bufferable 
[    2.626228] 	  Protection		: 0x2 -- Unprivileged, Non-Secure, Data Access
[    2.627313] 	  Access_Type		: Read
[    2.629372] device-mapper: uevent: version 1.0.3
[    2.630982] 	  Access_ID		: 0x15
[    2.630984] 	  Fabric		: cbb-fabric
[    2.635821] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel@redhat.com
[    2.638863] 	  Slave_Id		: 0x3
[    2.638864] 	  Burst_length		: 0x0
[    2.638864] 	  Burst_type		: 0x1
[    2.638865] 	  Beat_size		: 0x2
[    2.638866] 	  VQC			: 0x0
[    2.638867] 	  GRPSEC		: 0x7e
[    2.638868] 	  FALCONSEC		: 0x0
[    2.638870] 	**************************************

Removing the pinctrl entries under the i2c node allows to boot. Please find attached a device tree dump
dts_dpaux_i2c_mux_debug.txt (247.7 KB) from such a boot, as well as a kernel log dmesg_dpaux_i2c_mux_debug.txt (57.1 KB).

Under the Orin TRM, I only found this section:

2.23.6 UART6/UARTF
I/O pad: BDDPAUX_F3FCR90_VD181818NC
UART6 is muxed internally in LSIO with I2C6 that operates on DP-AUX-CH0. Mux Sel is configured in DPAUX_PINMUX_CFG_0 register. I2C6 would be used with DP Aux port and pinmux doesn’t exist for this. I 2 C vs Aux channel mode selection happens from a register bit field in DP registers. Interface has DP_AUX_CH0_P and DP_AUX_CH0_N pins. UART6 would use I 2 C mode of the DPAUX pad.

Which gives very little information about register addresses to check.

I’m running out of idea to make progress on this, while this topic is getting quite urgent on our side.

Looking forward to your support.

Hi,

The method on rel-35/rel-32 Xavier/TX2 may not work anymore. Let us do further check and share the info.

Hi @WayneWWW,

Thanks for your message and looking into it.

Best regards.

Hi,

Please try such configuration.

    i2c@31b0000 {

                             …

                             /* Add below lines */

                             pinctrl-names = "default";

                             pinctrl-0 = <&dpaux_default>;

              };

 

              miscreg@00100000 {

                             ...

                             /* Add below lines if we are using K5.10 */

                             compatible = "nvidia,tegra194-misc-dpaux-padctl";
                             dpaux_default: pinmux@0 {

                                           dpaux0_pins {
                                                          pins = "dpaux-0";
                                                          function = "i2c";

                                           };

                             };

 

                             /* Add below lines if we are using K5.15 */

                             compatible = "nvidia,tegra234-misc-dpaux-padctl";
                             dpaux_default: pinmux@0 {

                                           dpaux0_pins {

                                                          pins = "dpaux-0";

                                                          function = "i2c";

                                           };

                             };

              };

Dear @WayneWWW,

Thanks for the fast feedback, very much appreciated.
We are running JP5, so kernel 5.10. I was not successful with the patch you shared (I tried both variants just to be sure).

Is a special kernel config or some extra kernel patches required?

Please find below some excerpts of the boot log.
During boot, a lot of warnings like these appear:

[    0.002808] ------------[ cut here ]------------
[    0.002810] Tegra APB MISC not yet available
[    0.002862] WARNING: CPU: 0 PID: 1 at drivers/soc/tegra/fuse/tegra-apbmisc.c:75 tegra_read_chipid+0x3c/0x50
[    0.002864] Modules linked in:
[    0.002874] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.10.120-tegra #27
[    0.002879] pstate: 60400009 (nZCv daif +PAN -UAO -TCO BTYPE=--)
[    0.002881] pc : tegra_read_chipid+0x3c/0x50
[    0.002883] lr : tegra_read_chipid+0x3c/0x50
[    0.002884] sp : ffff80001004bc70
[    0.002885] x29: ffff80001004bc70 x28: 0000000000000000 
[    0.002888] x27: 0000000000000000 x26: 0000000000000000 
[    0.002891] x25: 0000000000000000 x24: 0000000000000000 
[    0.002893] x23: 0000000000000000 x22: ffffa7a8dbed6000 
[    0.002896] x21: ffff2233801449c0 x20: ffffa7a8dbed6db8 
[    0.002898] x19: ffffa7a8dbed6e00 x18: 0000000000000010 
[    0.002900] x17: 00000000b8d935b4 x16: 00000000ff5a2ac9 
[    0.002903] x15: ffff223380144f30 x14: ffffffffffffffff 
[    0.002905] x13: ffff80009004b917 x12: ffff80001004b921 
[    0.002907] x11: ffff8000100fa000 x10: 0140000000000000 
[    0.002910] x9 : ffff80001004bc70 x8 : 6e204353494d2042 
[    0.002912] x7 : 5041206172676554 x6 : c0000000ffffefff 
[    0.002915] x5 : 0000000000000000 x4 : 0000000000000000 
[    0.002917] x3 : 00000000ffffffff x2 : ffffa7a8dbb879c0 
[    0.002920] x1 : 6d6e009f41976e00 x0 : 0000000000000000 
[    0.002924] Call trace:
[    0.002926]  tegra_read_chipid+0x3c/0x50
[    0.002928]  tegra_init_revision+0x18/0x160
[    0.002938]  tegra30_fuse_init+0x70/0x158
[    0.002940]  tegra_init_fuse+0x158/0x1dc
[    0.002949]  do_one_initcall+0x4c/0x2d0
[    0.002954]  kernel_init_freeable+0x154/0x2d0
[    0.002965]  kernel_init+0x18/0x11c
[    0.002966]  ret_from_fork+0x10/0x18
[    0.002971] ---[ end trace 333d8a497195ee0d ]---

or:

[    0.003061] ------------[ cut here ]------------
[    0.003063] Tegra ABP MISC not yet available
[    0.003070] WARNING: CPU: 0 PID: 1 at drivers/soc/tegra/fuse/tegra-apbmisc.c:176 tegra_read_straps+0x40/0x60
[    0.003071] Modules linked in:
[    0.003073] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W         5.10.120-tegra #27
[    0.003077] pstate: 60400009 (nZCv daif +PAN -UAO -TCO BTYPE=--)
[    0.003078] pc : tegra_read_straps+0x40/0x60
[    0.003080] lr : tegra_read_straps+0x40/0x60
[    0.003081] sp : ffff80001004bc90
[    0.003082] x29: ffff80001004bc90 x28: 0000000000000000 
[    0.003084] x27: 0000000000000000 x26: 0000000000000000 
[    0.003087] x25: 0000000000000000 x24: 0000000000000000 
[    0.003090] x23: 0000000000000000 x22: ffffa7a8dbed6000 
[    0.003092] x21: ffff223380144f30 x20: ffffa7a8dbed6db8 
[    0.003095] x19: ffffa7a8dbed6e00 x18: 0000000000000010 
[    0.003097] x17: 00000000b8d935b4 x16: 00000000ff5a2ac9 
[    0.003099] x15: ffff223380144f30 x14: ffffffffffffffff 
[    0.003102] x13: ffff80009004b937 x12: ffff80001004b941 
[    0.003104] x11: ffff8000100fa000 x10: 0140000000000000 
[    0.003107] x9 : ffff80001004bc90 x8 : 6e204353494d2050 
[    0.003110] x7 : 4241206172676554 x6 : c0000000ffffefff 
[    0.003112] x5 : 0000000000000000 x4 : 0000000000000000 
[    0.003114] x3 : 00000000ffffffff x2 : ffffa7a8dbb879c0 
[    0.003117] x1 : 6d6e009f41976e00 x0 : 0000000000000000 
[    0.003120] Call trace:
[    0.003122]  tegra_read_straps+0x40/0x60
[    0.003124]  tegra30_fuse_init+0x94/0x158
[    0.003127]  tegra_init_fuse+0x158/0x1dc
[    0.003129]  do_one_initcall+0x4c/0x2d0
[    0.003131]  kernel_init_freeable+0x154/0x2d0
[    0.003133]  kernel_init+0x18/0x11c
[    0.003135]  ret_from_fork+0x10/0x18
[    0.003137] ---[ end trace 333d8a497195ee0f ]---

Eventually, a kernel panic occurs:

[   56.490193] Workqueue: events deferred_probe_work_func
[   56.495351] pstate: 60c00009 (nZCv daif +PAN +UAO -TCO BTYPE=--)
[   56.500960] pc : nvhost_syncpt_unit_interface_init+0x11c/0x1c0
[   56.507077] lr : nvhost_syncpt_unit_interface_init+0x108/0x1c0
[   56.512771] sp : ffff8000114dbb00
[   56.516438] x29: ffff8000114dbb00 x28: ffffc98abc8c6000 
[   56.521608] x27: ffff800010143ca8 x26: 0000000000000000 
[   56.527201] x25: 0000003ffc000000 x24: 0000000004000000 
[   56.532281] x23: ffff1424c4ccb080 x22: ffff1424c0aee010 
[   56.537789] x21: ffff1424c0aedcc0 x20: ffff1424c0aee000 
[   56.543043] x19: ffff1424c4694080 x18: 0000000000000010 
[   56.548639] x17: ffffc98abb45b310 x16: 0000000000000068 
[   56.553893] x15: ffff1424c3d8a2f0 x14: 6e69203a30787463 
[   56.559488] x13: 5f306f73696e3a78 x12: 6165727473282064 
[   56.564656] x11: 0000000000000000 x10: ffff4a9a722bc000 
[   56.570425] x9 : 0000000003fffe00 x8 : 0000000000200000 
[   56.575506] x7 : 0000000000000a20 x6 : ffff1424c4ca7ff8 
[   56.581101] x5 : 0000000000000009 x4 : ffff1424c4ca7000 
[   56.586270] x3 : 0000000004000000 x2 : ffffffffffffffff 
[   56.591862] x1 : 0000000000000000 x0 : ffffc98abcc2e000 
[   56.596944] Call trace:
[   56.599396]  nvhost_syncpt_unit_interface_init+0x11c/0x1c0
[   56.604989]  iommu_context_dev_probe+0x140/0x210
[   56.609539]  platform_drv_probe+0x58/0xb0
[   56.613740]  really_probe+0xf4/0x3d0
[   56.617239]  driver_probe_device+0x5c/0xc0
[   56.621264]  __device_attach_driver+0x88/0xc0
[   56.625295]  bus_for_each_drv+0x88/0xe0
[   56.629490]  __device_attach+0xf0/0x150
[   56.632996]  device_initial_probe+0x24/0x30
[   56.637021]  bus_probe_device+0x9c/0xb0
[   56.641039]  deferred_probe_work_func+0x88/0xc0
[   56.645767]  process_one_work+0x1c0/0x4a0
[   56.649791]  worker_thread+0x1f8/0x420
[   56.653293]  kthread+0x148/0x170
[   56.656791]  ret_from_fork+0x10/0x18
[   56.660467] Code: f9400a79 f9001279 9000bf40 b9487c01 (b9449342) 
[   56.666442] ---[ end trace 6f649019bd05d968 ]---
[   56.671143] Kernel panic - not syncing: Oops: Fatal exception
[   56.676831] SMP: stopping secondary CPUs
[   56.680687] Kernel Offset: 0x498aaad20000 from 0xffff800010000000
[   56.686716] PHYS_OFFSET: 0xffffebdc40000000
[   56.690830] CPU features: 0x08040006,4a80aa38
[   56.694947] Memory Limit: none
[   56.698097] ---[ end Kernel panic - not syncing: Oops: Fatal exception ]---

Could you tell us how you update the device tree? I feel the issue here is not related to the patch I shared.

It is more like you break the device tree. For example, what our patch added won’t affect tegra_read_chipid functionality.

Hi @WayneWWW,

I compile the device tree directly from the kernel build dir (using the dtbs make target) with ARCH, LOCALVERSION and CROSS_COMPILE variables set.

Then I scp the dtb file to the platform and copy it to the expected location.

I’m using a extlinux config with 2 entries. I keep one entry on a config known to boot (kernel image + dtb). The other extlinux config entry is used for testing.
I update the device tree on a daily basis for development purposes, so I’m quite sure that the right dtb lands on the disk. This is also how I revert to a working config. No reflashing was involved.

The kernel I’m using is the tag jetson 35.4.1 (version 5.10).

On a bootable configuration, my running Orin Nano shows from a dtc dump:

        miscreg@00100000 {
                compatible = "nvidia,tegra194-misc\0nvidia,tegra186-miscreg";
                status = "disabled";
                reg = <0x00 0x100000 0x00 0xf000 0x00 0x10f000 0x00 0x1000>;
        };

The matching driver (from the compatible string) would be at drivers/soc/tegra/fuse/tegra-apbmisc.c, and the source file part of the L4T release has the code:

u32 tegra_read_chipid(void)
{
        WARN(!chipid, "Tegra APB MISC not yet available\n");

        return chipid;
}
EXPORT_SYMBOL(tegra_read_chipid);

It does not look impossible that this error relates to the device tree change. Please let me know if my statements look incorrect to you.

Hi @WayneWWW,

Any update on this topic?

Best regards

Hi @maxe777

We will give you feedback later. Sorry for late reply.

Hi,

Could you try this? Add new node “miscreg-dpaux@00100000” instead of modifying the original one.


        miscreg-dpaux@00100000 {

                compatible = "nvidia,tegra194-misc-dpaux-padctl";

                reg = <0x0 0x00100000 0x0 0xf000>;

                dpaux_default: pinmux@0 {

                        dpaux0_pins {

                                pins = "dpaux-0";

                                function = "i2c";

                        };

                };

        };

 

        i2c@31b0000 {

                pinctrl-names = "default";

                pinctrl-0 = <&dpaux_default>;

        };

 

Hi @WayneWWW,

I just tested your last proposal and I confirm it resolves the issue.

Many thanks for the fast support, much appreciated.

Best regards

1 Like