This is a continuation of this previous ticket: Orin nano: muxing DP1_AUX as I2C
Summary:
- goal: have I2C functionality on Orin Nano on pins 98/100
- last reply from Nvidia: use the pinmux spreadsheet. But this is not effective since selecting I2C6 instead of DP_AUX_CH0 does not lead to any change in the generated DT files.
There are plenty of similar posts around, but for different platforms (TK1, TX1, TX2, Xavier NX and Xavier AGX).
Could you please share the procedure for the Orin Nana platform?
For reference, this is the DTS edit I tried:
i2c@31b0000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dpaux_default>;
};
host1x@13e00000 {
dpaux@155c0000 {
status = "okay";
compatible = "nvidia,tegra194-misc-dpaux-padctl";
reg = <0x0 0x155C0000 0x0 0xFFFF>;
dpaux_default: pinmux@0 {
dpaux0_pins {
pins = "dpaux-0";
function = "i2c";
};
};
};
};
Note the use of nvidia,tegra194-misc-dpaux-padctl since this this is what is referenced under kernel/nvidia/drivers/pinctrl/pinctrl-tegra234-dpaux.c under the .compatible field.
But this fails at boot:
[ 2.624869] tegra-i2c 31b0000.i2c: Adding to iommu group 2
[ 2.624963] **************************************
[ 2.625137] tegra-i2c 31c0000.i2c: Adding to iommu group 2
[ 2.625195] CPU:0, Error:cbb-fabric, Errmon:2
[ 2.625201] Error Code : TIMEOUT_ERR
[ 2.625360] tegra-i2c c250000.i2c: Adding to iommu group 2
[ 2.625414] Overflow : Multiple TIMEOUT_ERR
[ 2.625550] tegra-i2c 31e0000.i2c: Adding to iommu group 2
[ 2.625628]
[ 2.625883] Error Code : TIMEOUT_ERR
[ 2.625972] MASTER_ID : CCPLEX
[ 2.626048] Address : 0x155c4000
[ 2.626133] Cache : 0x1 -- Bufferable
[ 2.626228] Protection : 0x2 -- Unprivileged, Non-Secure, Data Access
[ 2.627313] Access_Type : Read
[ 2.629372] device-mapper: uevent: version 1.0.3
[ 2.630982] Access_ID : 0x15
[ 2.630984] Fabric : cbb-fabric
[ 2.635821] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel@redhat.com
[ 2.638863] Slave_Id : 0x3
[ 2.638864] Burst_length : 0x0
[ 2.638864] Burst_type : 0x1
[ 2.638865] Beat_size : 0x2
[ 2.638866] VQC : 0x0
[ 2.638867] GRPSEC : 0x7e
[ 2.638868] FALCONSEC : 0x0
[ 2.638870] **************************************
Removing the pinctrl entries under the i2c node allows to boot. Please find attached a device tree dump
dts_dpaux_i2c_mux_debug.txt (247.7 KB) from such a boot, as well as a kernel log dmesg_dpaux_i2c_mux_debug.txt (57.1 KB).
Under the Orin TRM, I only found this section:
2.23.6 UART6/UARTF
I/O pad: BDDPAUX_F3FCR90_VD181818NC
UART6 is muxed internally in LSIO with I2C6 that operates on DP-AUX-CH0. Mux Sel is configured in DPAUX_PINMUX_CFG_0 register. I2C6 would be used with DP Aux port and pinmux doesn’t exist for this. I 2 C vs Aux channel mode selection happens from a register bit field in DP registers. Interface has DP_AUX_CH0_P and DP_AUX_CH0_N pins. UART6 would use I 2 C mode of the DPAUX pad.
Which gives very little information about register addresses to check.
I’m running out of idea to make progress on this, while this topic is getting quite urgent on our side.
Looking forward to your support.