I2S sound in Jetpack4.2.2 L4T R32.2.1

yas_its · October 2, 2019, 6:16pm

How to enable I2S sound in Jetson Nano with Linux R32.2.1. After update driver tree in R32.1, it is working fine but not working in R32.2.1

jonathanh · October 3, 2019, 10:07am

Hello!

If you are using the I2S interface on the 40pin expansion header, you need to ensure that the pinmux is configured to enable the I2S interface. There is a application note available that describes the process for update the pinmux.

Regards,
Jon

yas_its · October 3, 2019, 12:03pm

Ok Thanks for reply

yas_its · October 4, 2019, 7:02pm

I have completed all the steps as per https://developer.nvidia.com/embedded/dlc/Jetson-Nano-40-Pin-Expansion-Header-1.1 , but device is not booting after ‘sudo ./flash.sh jetson-nano-qspi-sd mmcblk0p1’. Only ‘NVIDIA’ logo is coming. Kindly provide Solution.

Regards,

Yashwant

jonathanh · October 7, 2019, 8:17am

Hello!

We have identified a issue with the current pinmux spreadsheet for Nano where the MMC pins are not being correctly configured by default and preventing the device from booting. We are working to fix this. In the meantime, can you revert the changes you have made and make the following change only …

Sorry about this.

Regards,
Jon

BARO · October 8, 2019, 9:23am

Hello Jonathan . this problem was solved?

jonathanh · October 8, 2019, 9:36am

Hello!

I have not seen a new version published yet, but I will chase this.

Regards,
Jon

yas_its · October 8, 2019, 9:39am

Deaar Jon,
I have modified pinmux-config-p3450-porg.h as per direction, now I2S sound is working fine.

Regards,

Yashwant

yas_its · October 8, 2019, 9:49am

I2S4 and spi1 both enabled. Working pinmux-config-p3450-porg.h file is:
/*

Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
SPDX-License-Identifier: GPL-2.0+
*/

/*

THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
To generate this file, use the tegra-pinmux-scripts tool available from
https://github.com/NVIDIA/tegra-pinmux-scripts
Run “board-to-uboot.py nano”.
Used the T210_P3448_SKU0_pinmux sheet, tab B00-B01 as of 2 May 2019, v18.
NOTE: To WAR A01 <-> A02 Porg differences, I’ve edited this file.

  Removed DAP1/DAP4 pinmux programming as a WAR for A01 Porg.

Also, A02 <-> B00/B01 diff includes CLK_32K_OUT, which is NC on A02,
and CC7/I1 muxes/GPIOs (both OUT1).
*/

#ifndef PINMUX_CONFIG_P3450_PORG_H
#define PINMUX_CONFIG_P3450_PORG_H

#define GPIO_INIT(_port, _gpio, _init)
{
.gpio = TEGRA_GPIO(_port, gpio),
.init = TEGRA_GPIO_INIT##_init,
}

static const struct tegra_gpio_config p3450_porg_gpio_inits = {
/* port, pin, init_val */
GPIO_INIT(A, 5, IN),
GPIO_INIT(A, 6, OUT1),
GPIO_INIT(B, 4, IN),
GPIO_INIT(B, 5, IN),
GPIO_INIT(B, 6, IN),
GPIO_INIT(B, 7, IN),
GPIO_INIT(E, 6, IN),
GPIO_INIT(G, 2, IN),
GPIO_INIT(G, 3, IN),
GPIO_INIT(H, 0, OUT0),
GPIO_INIT(H, 2, IN),
GPIO_INIT(H, 3, OUT0),
GPIO_INIT(H, 4, OUT0),
GPIO_INIT(H, 5, IN),
GPIO_INIT(H, 6, IN),
GPIO_INIT(H, 7, OUT0),
GPIO_INIT(I, 0, OUT0),
GPIO_INIT(I, 1, OUT1),
GPIO_INIT(I, 2, OUT0),
GPIO_INIT(S, 5, IN),
GPIO_INIT(S, 7, OUT0),
GPIO_INIT(T, 0, OUT0),
GPIO_INIT(V, 0, IN),
GPIO_INIT(V, 1, IN),
GPIO_INIT(X, 3, OUT1),
GPIO_INIT(X, 4, IN),
GPIO_INIT(X, 5, IN),
GPIO_INIT(X, 6, IN),
GPIO_INIT(Y, 1, IN),
GPIO_INIT(Y, 2, IN),
GPIO_INIT(Z, 0, IN),
GPIO_INIT(Z, 2, IN),
GPIO_INIT(Z, 3, OUT0),
GPIO_INIT(CC, 4, IN),
GPIO_INIT(CC, 7, OUT1),
GPIO_INIT(DD, 0, IN),
};

#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, e_io_hv)
{
.pingrp = PMUX_PINGRP##pingrp,
.func = PMUX_FUNC##mux,
.pull = PMUX_PULL##pull,
.tristate = PMUX_TRI##tri,
.io = PMUX_PIN##io,
.od = PMUX_PIN_OD##od,
.e_io_hv = PMUX_PIN_E_IO_HV##_e_io_hv,
.lock = PMUX_PIN_LOCK_DEFAULT,
}

static const /* pingrp, PINCFG(PEX_L0_RST_N_PA0, PINCFG(PEX_L0_CLKREQ_N_PA1, PINCFG(PEX_WAKE_N_PA2, PINCFG(PEX_L1_RST_N_PA3, PINCFG(PEX_L1_CLKREQ_N_PA4, PINCFG(SATA_LED_ACTIVE_PA5, PINCFG(PA6, PINCFG(SPI2_MOSI_PB4, PINCFG(SPI2_MISO_PB5, PINCFG(SPI2_SCK_PB6, PINCFG(SPI2_CS0_PB7, PINCFG(SPI1_MOSI_PC0, PINCFG(SPI1_MISO_PC1, PINCFG(SPI1_SCK_PC2, PINCFG(SPI1_CS0_PC3, PINCFG(SPI1_CS1_PC4, PINCFG(SPI4_SCK_PC5, PINCFG(SPI4_CS0_PC6, PINCFG(SPI4_MOSI_PC7, PINCFG(SPI4_MISO_PD0, PINCFG(UART3_TX_PD1, PINCFG(UART3_RX_PD2, PINCFG(UART3_RTS_PD3, PINCFG(UART3_CTS_PD4, PINCFG(DMIC1_CLK_PE0, PINCFG(DMIC1_DAT_PE1, PINCFG(DMIC2_CLK_PE2, PINCFG(DMIC2_DAT_PE3, PINCFG(DMIC3_CLK_PE4, PINCFG(DMIC3_DAT_PE5, PINCFG(PE6, PINCFG(PE7, PINCFG(GEN3_I2C_SCL_PF0, PINCFG(GEN3_I2C_SDA_PF1, PINCFG(UART2_TX_PG0, PINCFG(UART2_RX_PG1, PINCFG(UART2_RTS_PG2, PINCFG(UART2_CTS_PG3, PINCFG(WIFI_EN_PH0, PINCFG(WIFI_RST_PH1, PINCFG(WIFI_WAKE_AP_PH2, PINCFG(AP_WAKE_BT_PH3, PINCFG(BT_RST_PH4, PINCFG(BT_WAKE_AP_PH5, PINCFG(PH6, PINCFG(AP_WAKE_NFC_PH7, PINCFG(NFC_EN_PI0, PINCFG(NFC_INT_PI1, PINCFG(GPS_EN_PI2, PINCFG(GPS_RST_PI3, PINCFG(UART4_TX_PI4, PINCFG(UART4_RX_PI5, PINCFG(UART4_RTS_PI6, PINCFG(UART4_CTS_PI7, PINCFG(GEN1_I2C_SDA_PJ0, PINCFG(GEN1_I2C_SCL_PJ1, PINCFG(GEN2_I2C_SCL_PJ2, PINCFG(GEN2_I2C_SDA_PJ3, PINCFG(DAP4_FS_PJ4, PINCFG(DAP4_DIN_PJ5, PINCFG(DAP4_DOUT_PJ6, PINCFG(DAP4_SCLK_PJ7, PINCFG(PK0, PINCFG(PK1, PINCFG(PK2, PINCFG(PK3, PINCFG(PK4, PINCFG(PK5, PINCFG(PK6, PINCFG(PK7, PINCFG(PL0, PINCFG(PL1, PINCFG(SDMMC1_CLK_PM0, PINCFG(SDMMC1_CMD_PM1, PINCFG(SDMMC1_DAT3_PM2, PINCFG(SDMMC1_DAT2_PM3, PINCFG(SDMMC1_DAT1_PM4, PINCFG(SDMMC1_DAT0_PM5, PINCFG(SDMMC3_CLK_PP0, PINCFG(SDMMC3_CMD_PP1, PINCFG(SDMMC3_DAT3_PP2, PINCFG(SDMMC3_DAT2_PP3, PINCFG(SDMMC3_DAT1_PP4, PINCFG(SDMMC3_DAT0_PP5, PINCFG(CAM1_MCLK_PS0, PINCFG(CAM2_MCLK_PS1, PINCFG(CAM_I2C_SCL_PS2, PINCFG(CAM_I2C_SDA_PS3, PINCFG(CAM_RST_PS4, PINCFG(CAM_AF_EN_PS5, PINCFG(CAM_FLASH_EN_PS6, PINCFG(CAM1_PWDN_PS7, PINCFG(CAM2_PWDN_PT0, PINCFG(CAM1_STROBE_PT1, PINCFG(UART1_TX_PU0, PINCFG(UART1_RX_PU1, PINCFG(UART1_RTS_PU2, PINCFG(UART1_CTS_PU3, PINCFG(LCD_BL_PWM_PV0, PINCFG(LCD_BL_EN_PV1, PINCFG(LCD_RST_PV2, PINCFG(LCD_GPIO1_PV3, PINCFG(LCD_GPIO2_PV4, PINCFG(AP_READY_PV5, PINCFG(TOUCH_RST_PV6, PINCFG(TOUCH_CLK_PV7, PINCFG(MODEM_WAKE_AP_PX0, PINCFG(TOUCH_INT_PX1, PINCFG(MOTION_INT_PX2, PINCFG(ALS_PROX_INT_PX3, PINCFG(TEMP_ALERT_PX4, PINCFG(BUTTON_POWER_ON_PX5, PINCFG(BUTTON_VOL_UP_PX6, PINCFG(BUTTON_VOL_DOWN_PX7, PINCFG(BUTTON_SLIDE_SW_PY0, PINCFG(BUTTON_HOME_PY1, PINCFG(LCD_TE_PY2, PINCFG(PWR_I2C_SCL_PY3, PINCFG(PWR_I2C_SDA_PY4, PINCFG(CLK_32K_OUT_PY5, PINCFG(PZ0, PINCFG(PZ1, PINCFG(PZ2, PINCFG(PZ3, PINCFG(PZ4, PINCFG(PZ5, PINCFG(DAP2_FS_PAA0, PINCFG(DAP2_SCLK_PAA1, PINCFG(DAP2_DIN_PAA2, PINCFG(DAP2_DOUT_PAA3, PINCFG(AUD_MCLK_PBB0, PINCFG(DVFS_PWM_PBB1, PINCFG(DVFS_CLK_PBB2, PINCFG(GPIO_X1_AUD_PBB3, PINCFG(GPIO_X3_AUD_PBB4, PINCFG(HDMI_CEC_PCC0, PINCFG(HDMI_INT_DP_HPD_PCC1, DP, PINCFG(SPDIF_OUT_PCC2, PINCFG(SPDIF_IN_PCC3, PINCFG(USB_VBUS_EN0_PCC4, PINCFG(USB_VBUS_EN1_PCC5, PINCFG(DP_HPD0_PCC6, PINCFG(PCC7, PINCFG(SPI2_CS1_PDD0, PINCFG(QSPI_SCK_PEE0, PINCFG(QSPI_CS_N_PEE1, PINCFG(QSPI_IO0_PEE2, PINCFG(QSPI_IO1_PEE3, PINCFG(QSPI_IO2_PEE4, PINCFG(QSPI_IO3_PEE5, PINCFG(CORE_PWR_REQ, PINCFG(CPU_PWR_REQ, PINCFG(PWR_INT_N, PINCFG(CLK_32K_IN, PINCFG(JTAG_RTCK, PINCFG(CLK_REQ, PINCFG(SHUTDOWN, }; struct pmux_pingrp_config p3450_porg_pingrps = {
mux, pull, tri, e_input, od, e_io_hv */
PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
SPI1, DOWN, NORMAL, OUTPUT, DISABLE, DEFAULT),
SPI1, NORMAL, TRISTATE, INPUT, DISABLE, DEFAULT),
SPI1, DOWN, NORMAL, OUTPUT, DISABLE, DEFAULT),
SPI1, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
SPI1, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
UARTC, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
UARTB, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
UARTD, UP, NORMAL, INPUT, DISABLE, DEFAULT),
I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
I2S4B, DOWN, NORMAL, OUTPUT, DISABLE, DEFAULT),
I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
UARTA, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
AUD, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
DP, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),

#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, hsm)
{
.drvgrp = PMUX_DRVGRP##_drvgrp,
.slwf = _slwf,
.slwr = _slwr,
.drvup = _drvup,
.drvdn = drvdn,
.lpmd = PMUX_LPMD##lpmd,
.schmt = PMUX_SCHMT##schmt,
.hsm = PMUX_HSM##_hsm,
}

static const struct pmux_drvgrp_config p3450_porg_drvgrps = {
};

#endif /* PINMUX_CONFIG_P3450_PORG_H */

BARO · October 8, 2019, 12:17pm

Hi

Did you modify only the h file without the files dtsi ? or you made all the process explained in the documentation to do it?
Because i have the screen with the NVIDIA logo after to made all the procedure to update the pinmux.

yas_its · October 8, 2019, 1:16pm

Sound will work only after updating of .h file.
for flushing the u-boot.bin, use following.

officeqm793 · October 2, 2020, 10:19pm

Hello Jon,

Is this issue ever been solved/fixed? I would like you to post a new documentation how to do this correctly at your earliest is possible.

Thank you,
Laszlo

maverich · November 18, 2020, 10:49am

link expired :/ is this issue resolved?

jonathanh · November 18, 2020, 11:05am

Hello!

If you are using the SD-card version of the Jetson Nano devkit and not the eMMC version, then you can use the jetson-io tool to configure the I2S signals …

$ sudo /opt/nvidia/jetson-io/config-by-function.py -o dtb i2s4
$ sudo reboot

For more details on jetson-io please see this doc.

The application note is no longer necessary because it has been superseded by this tool.

Regards
Jon

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I2S sound in Jetpack4.2.2 L4T R32.2.1

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