Is 1-lane MIPI CSI-2 on CSI-B (port-index=1, CAM0/J20) supported on Jetson Orin Nano?

Robotics & Edge Computing Jetson Systems Jetson Orin Nano
1

I’d like a definitive answer on whether 1-lane D-PHY reception on CSI-B (port-index=1) is supported on the Orin Nano Dev Kit (P3768-0000), or whether CAM0 effectively requires a 2-lane sensor.

Hardware

  • Jetson Orin Nano Dev Kit (P3768-0000 + P3767-0005-SUPER), L4T R36

  • ADV7282-M NTSC-to-MIPI bridge (1-lane D-PHY, discontinuous clock, 720×507 UYVY @ 30 fps)

  • ADV connected to J20 / CAM0

Device tree (relevant excerpt for the J20 sensor node)

adv7282-m@21 {
    compatible = "adi,adv7282-m";
    reg = <0x21>;
    num_lanes        = "1";
    bus-width        = <1>;
    lane_polarity    = "6";      
    discontinuous_clk = "yes";
    cil_settletime   = "0";
    /* port-index = <1> on the endpoint, VI + NVCSI legs matched */
};

Endpoints: port-index = <1> on the ADV endpoint, the matching NVCSI channel@0 input, and the VI input. Standard cam_i2cmux topology.

Symptom on J20 (failing)

v4l2-ctl streams open, then watchdog trips at 2.5s with zero frames captured:

[176.347933] tegra-camrtc-capture-vi: uncorr_err: request timed out after 2500 ms

Trace summary (repeats continuously):

rtcpu_nvcsi_intr: GLOBAL        type:PHY_INTR0 phy:0 cil:1 st:0 vc:0 status:0x00000008
rtcpu_nvcsi_intr: CORRECTABLE_ERR type:PHY_INTR  phy:0 cil:1 st:0 vc:0 status:0x00000008
capture_event_wdt: ts:...

Same sensor on J21 (working)

Same chain, moved to J21 / CAM1 with port-index = <2> and lane_polarity omitted (CSI-C, no module-level P/N swizzle). I get a clean 30 fps UYVY stream — ~22 MB / 8s, only intermittent corr_err: err_data 64/131072 frame discards. So the sensor, cable, and analog source are all good.

Questions

  1. Is 1-lane CSI-B (port-index=1) D-PHY reception a supported configuration on Orin Nano, or does CAM0 require a 2-lane sensor?

  2. If supported, is there a published reference DT for 1-lane CSI-B? (All the reference dtsi files I can find — IMX219, IMX477 — are 2-lane minimum on CSI-B.)

  3. For 1-lane operation on CSI-B specifically, is lane_polarity = "6" still the correct value, or does the bit interpretation differ from the 2-lane case?

Happy to attach full dmesg, trace, and the complete DT overlay on request.

Thanks.

5

Suppose there’s no problem to support 1 lane config. The config should be the same with imx219 but the bus-width is 1. Maybe check the HW to confirm the D0+/D0- of CSI-B is connect to correct lines.

Thanks

7

Thanks for the quick reply!

I have continued testing and I do not think the ADV7282-M board, analog input, or FPC implementation is the issue at this point.

The same ADV7282-M hardware and same analog video source work correctly when connected to J21 / CAM1. I have also tested both physical outputs from my ADV board into J21, and both produce valid video there:

ADV board output Jetson connector Result
J1 J21 / CAM1 Works
J2 J21 / CAM1 Works
J1 J20 / CAM0 Fails / no frames
J2 J20 / CAM0 Fails / LP / PHY errors

So both ADV outputs and both board-side pinouts have been verified using the known-good J21 path. The issue appears specific to receiving this 1-lane ADV7282-M stream on J20 / CAM0 / CSI-B.

For reference, my J20 connection is:

J20 pin 21  -> CSI1_D0_N
J20 pin 20  -> CSI1_D0_P
J20 pin 15  -> CSI1_CLK_N
J20 pin 14  -> CSI1_CLK_P

I2C is also working on J20. The ADV7282-M enumerates correctly, the driver binds, /dev/videoX is created, and v4l2-ctl can start streaming. The failure happens only after streaming starts, where VI times out with zero captured frames and the trace shows repeated NVCSI PHY interrupts.

The DT is configured as a 1-lane sensor. Relevant properties are:

num_lanes = "1";
bus-width = <1>;
discontinuous_clk = "yes";
cil_settletime = "0";

The endpoint port-index values are matched across the sensor endpoint, NVCSI input, and VI input. For J20 / CAM0 I am using port-index = <1>.

The main uncertainty is still the J20 / CSI-B lane mapping and polarity configuration for 1-lane operation.

On Orin Nano Dev Kit CAM0, the 2-lane reference camera DTS files use CSI-B with lane_polarity = "6". I originally carried that over, but I am not sure whether that same value is correct when only D0 and CLK are used.

Can you confirm the following for Orin Nano Dev Kit P3768-0000 / P3767?

  1. For a 1-lane D-PHY sensor on J20 / CAM0 / CSI-B, should the DT be identical to the IMX219-style CSI-B config except with bus-width = <1> and num_lanes = "1"?

  2. For 1-lane CSI-B, what is the correct lane_polarity value?
    Should it remain "6", or should it change because only CLK and D0 are active?

  3. Is the correct data lane for 1-lane CSI-B on J20 the physical pair labeled:

CSI1_D0_N / CSI1_D0_P

or does the NVCSI/DT logical lane mapping expect the single active lane on a different CSI-B data pair?

At this point I would like to rule out a DT lane mapping / polarity issue on CAM0 specifically. The ADV board and analog video path have been validated by moving the same hardware to J21, where the stream works.

I’ve attached the full overlay.

Thanks for the help!

overlay.txt (5.1 KB)